Texas Instruments ADS8365MEVM User manual

1 EVM Overview

1.1 Features

User's GuideSLAU189 – September 2006

ADS8364/65MEVM

This user's guide describes the characteristics, operation, and use of theADS8364/65MEVM 16-bit, parallel analog-to-digital converter evaluation module(EVM). A complete circuit description, a schematic diagram, and bill of materials isincluded.

Contents1 EVM Overview ...................................................................................... 12 Introduction .......................................................................................... 23 Analog Interface .................................................................................... 24 Digital Interface ..................................................................................... 45 Power Supplies ..................................................................................... 66 EVM Operation ...................................................................................... 67 EVM Bill of Materials, Assembly Drawing, and Schematic .................................... 78 Related Documentation From Texas Instruments ............................................ 10

List of Figures

1 Channel A0 Input Circuit ........................................................................... 32 Channel A1 Input Circuit ........................................................................... 43 ADS8364/654MEVM Assembly Drawing ........................................................ 9

List of Tables

1 Typical Analog Input Buffer Circuit Values ...................................................... 32 Header/Socket Combinations at J5 .............................................................. 53 J1 Pinout and Functions ........................................................................... 64 JP1 Pinout ........................................................................................... 65 ADS8364/65MEVM Jumpers ...................................................................... 76 ADS8364/65MEVM Bill of Materials ............................................................. 7

•Full-featured evaluation board for the ADS8364 and ADS8365 250-kHz, 16-bit, 6-channel,simultaneous-sampling, analog-to-digital converter•Analog inputs can be configured as single-ended or differential•Modular design allows direct connection to various DSP platforms through the 5-6K and HPA-MCUInterface Boards•Built-in reference•High-speed parallel interface

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2 Introduction

3 Analog Interface

3.1 Analog Input – Channel A0

Introduction

The ADS8364 and ADS8365 are high-speed, low-power, 6-channel, 16-bit A/D converters that operatefrom independent +5-V Avdd and Dvdd supplies. Internal buffer circuits powered from 3.3-V to 5.5-V BVddsupplies allow for mixed logic level operation without additional level translation.

The six input channels contain fully differential sample-and-hold circuits which are divided into three pairs(A, B, and C). Each channel pair has a hold signal (HOLDA, HOLDB, and HOLDC) which, when strobedtogether, provides simultaneous sampling on all six analog inputs. The devices accept analog inputvoltages in the range of –V

REF

to +V

REF

. The parts also accept bipolar input ranges when a level shiftcircuit is used in the analog front-end circuitry (see Figure 1 ).

Conversion time for the ADS8364 and ADS8365 is 3.2 µs when a 5-MHz external clock is used. Thecorresponding acquisition time is 800 ns. To achieve maximum output rate (250 kHz per channel, effective1.5-MSPS throughput max), the read function can be performed during the start of the next conversion.

The analog input to the EVM is divided in two parts. Connector J4 provides access to input channels A0and A1 through two different amplifier circuit configurations. The input buffer configuration of channel A0presents a typical front-end circuit for the A/D converter. Its function is to provide level and impedanceadaptation of the input signal. The input to channel A1 is a bipolar configuration using the INA159 toaccommodate ±10-V input signals. Connector J3 provides access to the remaining analog input channelsthrough simple R/C filters.

The analog input to the ADS8364/65MEVM board for channel A0 is composed of the dual OPA2132operational amplifier and its associated circuitry as shown in Figure 1 . The OPA2132 is powered from the±12-V analog supply, and arranged as an inverting amplifier with a gain of 1. The internal +2.5-Vreference voltage of the ADS8364 or ADS8365 is applied to the noninverting input of the OPA2132 toprovide input bias.

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3.2 Bipolar Input to Channel A0

Analog Interface

NOTE: Components marked NI are NOT INSTALLED.

Figure 1. Channel A0 Input Circuit

This configuration allows single-ended signals of ±2.5 V (+5 Vpp) to be applied to either input of channelA0 (J2 pin 1 or 3 referenced to pin 2). The input also can be applied to connector J4 (not shown) pins 2 or4, referenced to analog ground.

By changing components and setting the appropriate jumper, it is possible to configure the input buffer toaccept bipolar input voltages. Table 1 is related to the schematic presented in Figure 1 and represents justa few of the possible input configurations.

Table 1. Typical Analog Input Buffer Circuit Values

Input Voltage R3 R2 R1 R4 W2R28 R25 R24 R29 W1

Refer to Figure 1 Default open 5k Ω5k Ω5 k Ω1–20 – +50 – 2.5 5 k Ω5 k Ωopen 5 k Ω2–3– 2.5 – +2.5 20 k Ω4 k Ω20 k Ω4 k Ω2–3– 5 – +5 20 k Ω4 k Ω10 k Ω2 k Ω2–3– 10 – +10 20 k Ω4 k Ω5 k Ω1 k Ω2–3

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3.3 Analog Input – Channel A1

3.4 Analog Inputs –Channels B0/B1 and C0/C1

4 Digital Interface

Digital Interface

The output from the buffer stage in each case applies 0-5 V to the CHA0(+) input when the applied signalis connected to J2 pin 1 or J4 pin 2. The applied signal is directed to the CHA0(-) input when connectedvia J2 pin 3 or J4 pin 4.

When operating the ADS836x with single-ended signals, it is important to keep the unused ADC inputbiased to +2.5 V. This is easily accomplished on the EVM by changing the components associated witheither the inverting or noninverting input only, leaving the default component values shown in Table 1 onthe unused input. For example, to achieve a bipolar input range of ±10 V on CHA0(+), use the componentvalues shown for R1–R4 and move the shunt on W2 position 2-3. Components R24, R25, R28, and R29and the shunt on W1 should remain in the default conditions shown in Table 1 .

The analog input to the ADS8364/65MEVM board for channel A1 is composed of the INA159 differenceamplifier and the associated circuitry as shown in Figure 2 . The INA159 is powered from the +5-V analogsupply, and arranged as a noninverting amplifier with a gain of 0.2. The internal +2.5-V reference voltageof the ADS836x is applied to both REF1 and REF2 pins of the INA159 to provide a direct ±10-V interfacewith built-in level translation to the noninverting input of channel A1.

Figure 2. Channel A1 Input Circuit

The analog inputs to the remaining ADS836x input channels are routed to connector J3 and configuredwith simple R/C filters only. This configuration allows the EVM user to apply any customized input circuit tothe data converter. Connector J3 is composed of a male/female pass-through combination of pin headerand socket with industry standard 0.1-inch centers.

When the ADS8364/65MEVM is used in combination with the 5-6K Interface Board or HPA-MCU InterfaceBoard, the DAP Signal Conditioning Board (SLAU105 ) can be used to drive the remaining input channels.

The ADS8364/65MEVM is designed for easy interfacing to multiple control platforms. Jumper options areprovided on the EVM to allow control over the state of Chip Select pin ( CS) as well as the operating modepins (A0–A2), the Reset pin ( RST), and the Conversion Start strobes (HOLD A, HOLDB, and HOLDC).

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4.1 Parallel Control

4.2 Parallel Data

4.3 GPIO/Control Options

Digital InterfaceJumpers W4 and W6 control the signals applied to A0, A1, A2, and CS. In the factory default mode, W6 isclosed by means of a shunt jumper. The Ax and CS pins are controlled by the signals applied to J5 (top orbottom side). When used with either the 5-6K or HPA-MCU Interface Boards, these control signals areassociated with the host processors address bus.

By removing the shunt jumper located at W6, the A0, A1, and A2 pins are controlled by shunt jumpersplaced on W4. The CS pin is routed to J5.1, which requires the application of an active-low Chip Selectsignal. A simple shunt jumper placed across J5 pins 1-2 can be used to force the CS pin to ground ifdesired.

Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 10-pin,dual-row, header/socket combination at J5 (Table 2 ). This header/socket provides access to the digitalcontrol pins of the EVM. Consult Samtec at www.samtec.com or 1-800-SAMTEC-9 for a variety of matingconnector options.

Table 2. Header/Socket Combinations at J5

Pin Number Signal Description

J5.1 DC_CSa Daughter Card Chip Select – active-low signal used to access the EVMJ5.3 DC_AWE Write Strobe – signal not used on the ADS8364/65M EVMJ5.5 DC_ARE Read Strobe – active-low signal used to access parallel dataJ5.7 EVM_A0 EVM Address line 0 – used with U3 to control A0J5.9 EVM_A1 EVM Address line 1 – used with U3 to control A1J5.11 EVM_A2 EVM Address line 2 – used with U3 to control A2J5.13 EVM_A3 EVM Address line 3 – used with U3 and U6 to control CSJ5.15 EVM_A4 EVM Address line 4 – not usedJ5.17 DC_TOUT Timer Input – optional CLK input used with W8J5.19 DC_INTa Interrupt Output to Host Processor – connects to the ADC EOC pin

The ADS8364/65MEVM uses Samtec part numbers SSW-116-22-F-D-VS-K and TSM-116-01-T-DV-P toprovide a convenient 16-pin, dual-row header/socket combination at J6. This header/socket combinationprovides access to the parallel data pins of the ADS7864. Data line D0 is connected to J6 pin 1. Datalines 1–15 are located on pins 3–31, respectively. Even pin numbers 2–32 are connected to digital ground.

Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a 10-pin, dual-row,header/socket combination at J1 to facilitate general-purpose input/output (GPIO) control options to theADS836x device installed on the EVM. Table 3 describes the functions and pinout of J1.

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5 Power Supplies

5.1 Reference Voltages

6 EVM Operation

Power Supplies

Table 3. J1 Pinout and Functions

Pin Number Signal Description

J1.1 NAP Controls power-down options on the ADS8365 (only) using the NAP input pinJ1.3 ADD Controls read options, when HI, address information can be read from the chipJ1.5 HOLD_C# Active-low signal HOLDC used to start a conversion on ADC channel pair CJ1.7 HOLD_B# Active-low signal HOLDB used to start a conversion on ADC channel pair BJ1.9 HOLD_A# Active-low signal HOLDA used to start a conversion on ADC channel pair AJ1.11 RESET# Active-low signal RESET used to place the ADS7864’s FIFO in reset stateJ1.13 NA Unused on the ADS8364/65MEVMJ1.15 NA Unused on the ADS8364/65MEVMJ1.17 DC_TOUTa Used with W10 to allow host processor timer control of HOLDxJ1.19 NA Unused on the ADS8364/65MEVM

The ADS8364/65MEVM board requires +5 VDC for the both the analog and digital section of the ADC.The supply (+Va and +Vd) can range from +4.75 VDC to +5.25 VDC. . The internal buffer can be poweredthrough the BVdd input voltage and can range from 2.7 VDC to 5.5 VDC. Because the EVM is designed towork with the 5-6K and HPA-MCU Interface Boards, JP1 provides direct connection to the common powerbus described in SLAU104 .

Table 4 shows the pinout of JP1:

Table 4. JP1 Pinout

Signal Pin Number Signal

+VA (positive input buffer supply) 1 2 -VA (negative input buffer supply)+5VA (+Va to the ADS8364) 3 4 -5VA (Unused)DGND 5 6 AGND+1.8VD (Unused) 7 8 +VD1 (Unused)+3.3VD (used with W5 for support circuitry) 9 10 +5VD (+5V to pin 22 of the ADS8364 and pin 22 of theADS8365)

Alternate power sources can be applied via various test points located on the EVM. See the schematic atthe end of this document for details. Note – while filters are provided for all power supply inputs, optimalperformance of the EVM requires a clean, well-regulated power source.

The ADS8364/65MEVM is configured to use its internal reference through jumper W3 (see schematic fordetails). If an external reference is desired, the shunt jumper on W3 should be moved to cover pins 1-2;the external reference source can be applied to the test point labeled TP10 referenced to TP12. Theinternal +2.5-V reference is still connected to the input buffer U1 in this case to ensure proper mid-pointbiasing to channel A1.

The analog input swing is 5 Vpp, centered on a +2.5-V internal or external reference. The installed deviceaccepts bipolar input ranges when a level shift circuit is used in the analog front-end circuitry. Forinformation on various circuit configurations, see section 3.2 of this document or section 12 of Op-Ampsfor Everyone (SLOD006 ) .

Once power is applied to the EVM, the analog input source can be connected directly to J3 or J4 (top orbottom side) or through optional amplifier and signal-conditioning modules using the 5-6K and HPA-MCUInterface Boards. The analog input level should not exceed 5 Vp-p. The analog input range is from ±Vref(typically 2.5 VDC) centered at +2.5 V.

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6.1 Default Jumper Locations

7 EVM Bill of Materials, Assembly Drawing, and Schematic

7.1 Bill of Materials

EVM Bill of Materials, Assembly Drawing, and SchematicThe digital control signals can be applied directly to J1 and J5 (top or bottom side). TheADS8364/65MEVM can also be connected directly to the 5-6K Interface Board for use with a variety ofC5000™ and C6000™ series DSP Starter Kits (DSK), or the HPA-MCU Interface Board for use withC2000™ Series DSPs and TMS470™ Series controllers. The Control and Data connectors are designedto allow pattern generators and/or logic analyzers to be connected to the EVM using standard ribbon-typecables on 0.1-inch centers.

The BYTE signal, which controls the output of the ADS836x when used with 8-bit controllers, can bemanipulated with jumper W7. By default, W7 is closed and the BYTE pin is held low, providing data in16-bit format. Removing the shunt at W7 asserts BYTE high by means of pullup resistor R23.

The conversion clock can be applied to J7, a BNC connector with a 50- Ωterminator, or J5 as mentionedpreviously. Jumper W8 allows the EVM user to select the clock source. In normal operation (factorydefault) the shunt on jumper W8 is covering pins 2-3. To use a clock source applied to the BNC connectorJ7, move the shunt at jumper W8 to cover pins 1-2. In either case, the conversion clock can be monitoredat TP21.

Table 5 provides a list of jumpers found on the EVM and their factory default conditions.

Table 5. ADS8364/65MEVM Jumpers

Jumper Shunt Position Jumper Description

W1 Pins 1-2 Controls CHA1(+) input source selectionW2 Pins 1-2 Controls CHA1(–) input source selectionW3 Pins 2-3 Controls reference source (default is internal)W4 OPEN 3x2 Jumper to control A0, A1, A2W5 Pins 1-2 Controls BVdd SelectionW6 Closed Controls application of A0, A1 and A2 signals as well as the chip select input. Used in conjunctionwith W4.W7 Closed Controls BYTE input, opening W7 forces BYTE high via R23W8 Pins 2-3 Controls application of conversion clock source via J5 or J7W9 NA W9 pins 2-3 are wired short on the PWBW10 TIMER 3×3 Jumper to control HOLDx signals – timer or GPIO options available

Table 6 contains a complete Bill of Materials for the ADS8364/65MEVM.

Table 6. ADS8364/65MEVM Bill of Materials

Designators Description Manufacturer Mfg. Part Number

C2 C3 C7 C10–C12 0.1uF, 0603, Ceramic, X7R, 25V, 10% TDK Corp. C1608X7R1E104KC18 C37–C39 C41C45–C49 C52C35 C36 C42–C44 1nF, 0603, Ceramic, COG, 50V, 5% TDK Corp. C1608C0G1H102JC53

C5 C6 C8 C9 C13 10 µF, 0805, Ceramic, X5R, 16V, 10% Taiyo Yuden EMK212BJ106KG-TC15

C1 C19 33pF, 0805, Ceramic, COG, 50V, 5% TDK Corp. C1608C0G1H330JC22 C24 0.01 µF, 0603, Ceramic, COG, 25V, 5% TDK Corp. C1608C0G1E103JC16 C14 C25–C34 100pF, 0603, Ceramic, COG, 50V, 5% TDK Corp. C1608C0G1H101JC50 1 µF, 0603, Ceramic, X7R, 16V, 10% TDK Corp. C1608X7R1C105K

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EVM Bill of Materials, Assembly Drawing, and Schematic

Table 6. ADS8364/65MEVM Bill of Materials (continued)

Designators Description Manufacturer Mfg. Part Number

D1 D2 Green LED Chicago Miniature CMD15-21VGC/TR8J1 J3–J5(Bottom 10 Pin, Dual Row, SMT Socket (20 Pos.) Samtec SSW-110-22-S-D-VSSide)

J1 J3–J5 (Top Side) 10 Pin, Dual Row, SMT Header (20 Pos.) Samtec TSM-110-01-T-D-V-PJ2 3 Terminal Screw Connector On-Shore Tech. ED555/3DSJ6 (Bottom Side) 16 Pin, Dual Row, SMT Socket (32 Pos.) Samtec SSW-116-22-S-D-VSJ6 (Top Side) 16 Pin, Dual Row, SMT Header (32 Pos.) Samtec TSM-116-01-T-D-V-PJ7 PCB Mount BNC Amphenol 31-5329JP1(Bottom Side) 5 Pin, Dual Row, SMT Socket (10 Pos.) Samtec SSW-105-22-S-D-VSJP1 (Top Side) 5 Pin, Dual Row, SMT Header (10 Pos.) Samtec TSM-105-01-T-D-V-PFB1–FB5 0805 size Ferrite Bead TDK Corp. MMZ2012D121BR1 R2 R4 R24 R25 4.99k Ω, 1%, 0805, .1W Resistor Yageo Corp. 9C08052A4991FKHFTR29

R5–R14 R20 R21 49.9 Ω, 0603, 1%, 0.1W Resistor Yageo Corp. RC0603FR-0749R9LR31 R36R16–R19 R22 R23 10k Ω, 0603, 5%, 0.1W Resistor Yageo Corp. RC0603JR-0710KLR34 R35R26 R27 2k Ω, 0805, 0.1W Resistor Yageo Corp. 9C08052A2001JLHFTR15 R32 0 Ω, 0603, 0.1W Resistor Yageo Corp. RC0603JR-070RLTP1–TP3 TP8 Tp9 Red Test Point Loop Keystone 5000TP10 TP20AGND DGND TP12 Black Test Point Loop Keystone 5001TP11 TP13–TP17 SMT Test Point Loop – Shown on Silkscreen as: A0, Keystone 5015TP21–TP24 A1, A2, RST, RD, WR, CS, CLOCK, FD, EOCU1 OPA2132, SOIC Texas Instruments OPA2132UAU2 OPA2340; DGK package Texas Instruments OPA2340EAU4 ADS8364 Texas Instruments ADS8364Y/250U5 INA159; DGK package Texas Instruments INA159AIDGKRU3 SN74CBT3257PW Texas Instruments SN74CBT3257PWRU6 SN74AHC1G04 Texas Instruments SN74AHC1G04DBVTU7 SN74AHC125 Texas Instruments SN74AHC125PWW1–W3 W5 W8 3 Pin Header Samtec TSW-103-07-L-SW6 W7 2 Pin Header Samtec TSW-102-07-L-SW4 2 ×3 Header Samtec TSW-103-07-L-DW10 3 ×3 Header Samtec TSM-103-07-L-TC4 C17 C20 C21 Not InstalledC23 C51 R3 R28R33 W9

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7.2 Assembly Drawing

7.3 Circuit Schematics

EVM Bill of Materials, Assembly Drawing, and Schematic

Figure 3 shows the top layer of the ADS8364/65MEVM and provides quick access to componentdesignator found on the PWB. Complete Gerber files are available on request.

Figure 3. ADS8364/654MEVM Assembly Drawing

The entire circuit schematic for the ADS8364/65MEVM appears on the following page.

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123456

54321

Ati

12500 TI Boulevard. Dallas, Texas 75243

Title:

SHEET: OF:

FILE:

SIZE: DATE: REV:

14-Jul-2006

Drawn By:

Engineer:

Revision History

REV ECN Number Approved

mADS8364_2_SH1.Sch

8 4

U1A

OPA2132

+Vin

-Vin

4.99K

33pF

Vref

TP7

U1B

OPA2132

R29

4.99K

R25

4.99K

R28

R24

4.99K

C19

33pF

C20

NI Vref

TP6

A0+

A0-

B0+

B0-

C0+

C0-

B1+

B1-

C1+

C1-

C24

0.01uF

C22

0.01uF

C23

C21

+Vin

-Vin

Op Amp Bypass

49.9

R12

49.9

R11

49.9

R10

49.9

R14

49.9

R13

49.9

Tom Hendrick

Tom Hendrick B A

ADS8364/65 Modular Evaluation Module

C30

100pF

C31

100pF

C28

100pF

C27

100pF

C34

100pF

C29

100pF

C33

100pF

C32

100pF

C25

100pF

C26

100pF

C44

1nF

A0In

C43

1nF

C36

1nF

C42

1nF

C35

1nF

Note:

Components marked "NI"

are NOT installed!

Analog Input

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20

Analog Input

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20

IN+

V-

REF2 8

V+ 7

OUT 6

SENSE 5

IN-

REF1

1U5

INA159

Vref

R21

49.9

C16

100pF

A1+

AVdd

C18

0.1uF

R20

49.9

C14

100pF

A1-

Wire Short

R33

AVdd

C17

C51

C50

1uF

C53

1nF

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