ST STM32F0 Series Installation and operating instructions

May 2012 Doc ID 022837 Rev 1 1/17

AN4055

Application note

Clock configuration tool for STM32F0xx microcontrollers

Introduction

This application note presents the clock system configuration tool for the STM32F0xx

microcontroller family.

The purpose of this tool is to help the user configure the microcontroller clocks, taking into

consideration product parameters such as power supply and Flash access mode.

The configuration tool is implemented in the “STM32F0xx_Clock_Configuration_VX.Y.Z.xls”

file which is supplied with the STM32F0xx Standard Peripherals Library and can be

downloaded from www.st.com.

This tool supports the following functionalities for the STM32F0xx:

●Configuration of the system clock, HCLK source and output frequency

●Configuration of the Flash latency (number of wait states depending on the HCLK

frequency)

●Setting of the PCLK1, PCLK2, TIMCLK (timer clocks) and I2SCLK frequencies

●Generation of a ready-to-use system_stm32f0xx.c file with all the above settings

(STM32F0xx CMSIS Cortex-M0 Device Peripheral Access Layer System Source File)

The STM32F0xx_Clock_Configuration_VX.Y.Z.xls is referred to as “clock tool” throughout

this document.

Before using the clock tool, it is essential to read the STM32F0xx microcontroller reference

manual (RM0091). This application note is not a substitute for the reference manual.

This tool supports only the STM32F0xx devices.

For VX.Y.Z, please refer to the tool version, example V1.0.0

www.st.com

Contents AN4055

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Contents

1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Software requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Hardware requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2.2 Clock scheme for STM32F0xx microcontrollers . . . . . . . . . . . . . . . . . . . 7

2.2.3 I2S clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Tutorials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 Wizard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2 Expert mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4 Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

AN4055 List of tables

Doc ID 022837 Rev 1 3/17

List of tables

Table 1. Definition of terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 2. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

List of figures AN4055

4/17 Doc ID 022837 Rev 1

List of figures

Figure 1. Clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2. I2S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3. Wizard mode user interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4. Select the clock source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. File generation error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6. Expert mode user interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 7. System clock frequency is exceeded . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

AN4055 Glossary

Doc ID 022837 Rev 1 5/17

1 Glossary

Table 1. Definition of terms

Term Description

HCLK AHB clock

PCLK1 APB1 clock

PCLK2 APB2 clock

TIMCLK Timer clock

FCPU Cortex-M0 clock

Ext.Clock External clock

VDD Power supply

HSI High-speed internal clock

HSE High-speed external clock

MCLK Master clock

I2S Integrated interchip sound

Fs Sampling frequency

I2SCLK I2S clock

Getting started AN4055

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2 Getting started

This section describes the requirements and procedures needed to start using the clock

tool.

2.1 Software requirements

To use the clock tool with Windows®operating system, a recent version of Windows, such

as Windows XP, Vista or Windows 7 must be installed on the PC with at least

256 Mbytes of RAM.

Before starting to use the clock tool, make sure that Microsoft®Office is installed on your

machine and then follow these steps:

●Download the latest version of the clock tool for the STM32F0xx product from

www.st.com.

●Enable macros and ActiveX®controls:

Excel®

1997-2003 version

1. Click Tools in the menu bar.

2. Click Macro.

3. Click Security.

4. Click Low (not recommended).

Note: If ActiveX controls are not enabled, a warning message is displayed asking you to enable

ActiveX. In this case, you should click “OK” to enable it.

Excel 2007 version

1. Click the Microsoft Office button and then click Excel options.

2. Click Trust Center, click Trust center settings, and then click Macro settings.

3. Click Enable all macros (not recommended, potentially dangerous code can run).

4. Click Trust Center, click Trust center settings, and then click ActiveX settings.

5. Click Enable all controls without restrictions and without prompting (not

recommended; potentiality dangerous controls can run).

6. Click OK.

Note: For more information about how to enable macros and ActiveX controls please refer to the

Microsoft Office website.

AN4055 Getting started

Doc ID 022837 Rev 1 7/17

2.2 Hardware requirements

2.2.1 Introduction

The clock tool is designed to configure the system clocks and generate the

system_stm32f0xx.c file for STM32F0xx microcontrollers.

The system_stm32f0xx.c file is provided as a template system clock configuration file which

can be easily modified to select the corresponding system clock frequency and to configure

the Flash latency.

2.2.2 Clock scheme for STM32F0xx microcontrollers

This section describes the system clock scheme that is dependent on the voltage

requirements (VDD ) versus the system clock frequency and Flash latency versus the system

clock frequency.

Three different clock sources can be used to drive the system clock (SYSCLK):

1. HSI (8 MHz) oscillator clock

2. HSE (4 MHz to 32 MHz) oscillator clock

3. Main phase-locked loop (PLL) clock with a PLL voltage-controlled oscillator

(PLLVCO) input frequency.

All peripheral clocks are derived from the SYSCLK.

Note: The number of Flash memory wait states (latency) is defined according to the frequency of

the CPU (Cortex-M0):

- Zero wait states if 0 < SYSCLK <= 24 MHz

- One wait state if SYSCLK > 24 MHz

Getting started AN4055

8/17 Doc ID 022837 Rev 1

Figure 1. Clock scheme

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AN4055 Getting started

Doc ID 022837 Rev 1 9/17

2.2.3 I2S clock generator

This section describes the I2S clock generator. It is dependent on:

●Master clock MCLK (enable or disable)

●Frame width

●I2S peripheral clock (I2SCLK).

Figure 2. I2S clock generator architecture

The audio sampling frequency may be 192 kHz, 96 kHz, 48 kHz, 44.1 kHz, 32 kHz,

22.05 kHz, 16 kHz, 11.025 kHz or 8 kHz. To reach the desired frequency, the linear divider

(DIV) needs to be programmed according to the formulas below:

When the master clock is generated (MCKOE bit in the SPI_I2SPR register is set):

●FS = I2SxCLK/[(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16 bits wide

●FS = I2SxCLK/[(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32 bits wide

Where ODD is an odd factor for the prescaler.

When the master clock is disabled (MCKOE bit cleared):

●FS = I2SxCLK/[(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16 bits wide

●FS = I2SxCLK/[(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32 bits wide

Note: This tool does not configure the I2S register.

The sampling frequency error is computed as an indicator according to the I2S parameters

which are not configured in the output file “system_stm32f0xx.c”.

8-bit

divider +

linear

ODD I2SDIV[7:0]

I2SxCLK

CHLENI2SMOD

reshaping stage

Divider by 4 Div2

MCKOE

MCK

Tutorials AN4055

10/17 Doc ID 022837 Rev 1

3 Tutorials

This section describes how to use the clock tool to configure all system clocks and generate

the system_stm32f0xx.c file. Two modes are available: Wizard and Expert. The selection is

made in the Configuration mode list box.

3.1 Wizard mode

This mode (default mode) guides you through a series of steps to obtain the desired clock

system configuration quickly and easily.

Figure 3. Wizard mode user interface

Note: The ‘Reset’ button permits the system clock for the default configuration to be set.

The wizard guides you through the following steps:

1. Set the HSE frequency (if is used in your application) between a minimum of 4 MHz,

and a maximum of 32 MHz if a crystal oscillator is used for the STM32F0xx. If the

frequency entered is out of range, an error message is displayed, and a valid frequency

must be entered.

The definition of HSE_VALUE in the stm32f0xx.h file must be modified each time the

user changes the HSE oscillator value.

2. Configure the Prefetch buffer (select ON or OFF from the list box).

3. Specify if the I2S clock is needed. If needed, enable it and follow steps 7, 8 and 9.

Otherwise, go to step 4.

4. Set the desired HCLK frequency. If the value entered is higher than the maximum

HCLK frequency, an error message is displayed.

5. Select the PCLK1 and PCLK2 prescaler settings from the list box to obtain the desired

PCLK1 and PCLK2 frequencies. The TIMCLK frequencies are configured automatically

depending on the PCLK1 and PCLK2 prescaler settings.

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