Sharp OZ-9600II User manual

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1

Table of contents

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OZ-9600

II

IQ-9200

SHARP

SERVICE

MANUAL

STANDARD

FUNCTION

10

digits

1M

DISPLAY SECTION

ELEMENT:

DISPLAY:

FSTN

LCD

320

x

240

dot

matrix

liquid

crystal

display

LSI

CPU:

LH58061M

Display:

LF7713Q

RTC:

SMC5245

POWER

SUPPLY

AG:X

DC:O

Main

power

supply:

6

Vde

Alkaline

batteries

(LRO3

x

4)

Memory

backup

power:

3

Vdc

lithium

battery

(CR2032

x

1)

POWER

CONSUMPTION

0.31

W

AUTO

POWER

OFF

TIME

12

minutes

MEMORY

PROTECT

Yes

DIMENSIONS(mm)

Open:

=

180(W)

x

210(D)

x

14.2(H)

mm.

7-3/32"(W)

x

8-9/32"(D)

x

9/16"(H)

Closed:

180(W)

x

105(D)

x

25.4(H)

mm.

7-3/32"(W)

x

4-1/8"(D)

x

1"(H)

Weight

Approx.

430g

CALCULATIONS

Functions:

addition,

subtraction,

multiplication,

division;

constant,

square

root,

percent,

memory

calculation,

date

calculation,

paperless

printer.

Digits:

10

digits

Serial

input/output

Type

of

transmission:

Asynchronoushalf-duplex/fullduplex

Transmission

speed:

300,

600,

1200, 2400,

4800,

9600

bps

Parity

bit:

even,

odd,

none

Word

length:

7

or

8

bits

Stop

bit:

1

or

2

bits

Connector

used:

15-pin

connector

Output

signal

level:

©

C-MOS

level

(4

to

6

volts)

Interface

signals:

Input;

RD,

CS,

CD, DR,

CI

Output;

SD,RS,

RR,

ER

Other;

.SG,

VC,

FG

Operating

temperatures

0°C

to

40°C

(32°

to

104°F)

Peripherals

and

transfer

interface

IR

transfer

Up

to

a

distance

of

approx.

80

cm.

Cable

jack

15-pin

IC

card

slot

1

Parts

marked

with

"A\”

is

important

for

maintaining

the

safety

of

the

set.

Be

sure

to

replace

these

parts

with

specified

ones

for

maintaining

the

safety

and

performance

of

the

set.

SHARP

CORPORATION

CODE:

00Z0Z96002SME

OZ-9600II

mopeL

1Q-9200

Electronic

Organizer

notebook

section

.

Applications

Calendar,

Schedule,

To

Do,

Anniversary,

Telephone,

User

File,

Notebook,

Outline,

Scrapbook,

Filter

Memory

capacity

512

Kbytes

(User

area:

Approx.

381

Kbytes)

Schedule

application

capacity:

:

Approx.

6,730

entries

consisting

of

an

averge

of

32

charactes

Tel

application

capacity:

Approx.

6,610

entries

consisting

on

averge

of

16

charactes

in

the

name

field

and

12

in

the

number

field

These

capacities

only

apply

when

all

the

available

memory

is

committed

to

a

single

function.

Maximum

Notebook:

16

Kbytes

data

size

per

Outline:

32

Kbytes

for

an

entire

outline

entry

2

Kbytes

for

each

topic

Tel/User

File:

2

Kbytes

for

text

data

61.7

Kbytes

for

graphics

data

Other

applications:

2

Kbytes

User

interfaces

Touch

panel,

keyboard

Other

features

Secret

function,

data

transfer,

search

Clock

Crystal

oscillation

frequency:

32,768

Hz

Clock

precision:

Average

variance

per

day,

1.5

seconds

(at

25°C/77°F)

Content

of

displays:

year,

month,

day,

day

of

week,

hours,

minutes,

A.M./P.M.,

city

names

:

Time

system:

12-hour

and

24-hour

clock

World

clock

function:

Display

of

date

and

time

for

the

world’s

cities.

Enable/dis-

able

daylight

saving

time

display

function.

Operating

time

Battery

life

may

vary

depending

on

usage.

Operating

batteries:

When

alkaline

batteries

are

used:

@

Approx.

80

hours

(2.5

months

of

1

hour

continuous

use

per

day)

Continuous

display

at

an

ambient

temperature

of

20°C

(68°F)

©

Approx.

70

hours

(2

months

of

1

hour

continuous

use

per

day)

Searching

data

for

5

minutes

and

display

on

for

55

minutes

per

hour,

at

an

ambient

temperature

of

20°C

(68°F)

The

battery

life

may

be

shorter

than

the

above

when

manganese

batteries

are

used.

Memory

backup

battery:

:

Approx.

5

years

(regardless

of

the

condition

of

the

operating

batteries)

Accessories

Alkaline

batteries

(LRO3

x

4)

Lithium

batteries

CR2032

(installed)

Touch

pen,

Operation

manual,

protection

card

This

document

has

been

published

to

be

used

for

after

sales

service

only.

The

contents

are

subject

to

change

without

notice.

OZ-9600II

IQ-9200

KEY

LAYOUT

@

USA

(OZ960011)

®

UK

(IQ-9200)

.

19-9200

512KB

SS

5

J

ee

Sateee

ante

0

DO@MDaWMMMmmsas

(2oe)

ki

caress

0

G3

G2

G4

5

Cs)

GC

C2

Co

Cs).

ealicajesis

slealea|eaieale

eck

ccoftaleaieajesleatea

[eal

reay

HEH

MMOWHE|

|

wAebimmec

cc

qje

BAM

PMOMMAEM)

|

BoMmeMeawwoow@

(a)

(i)

fo

i)

(ase)

(oe)

(Hm)

Caen)

(Ces)

Ce)

fe)

oo]

se)

C8)

Ga)

Cee)

@

Except

USA,

UK

(IQ-9200)

sual

FHTILE

[letter

to

wr.sith

]

PAGE

1/5

FROM:

:

Michael

Carson

»

Ar

4

;

:

LARGE!

f

.

H_exnertence

{

=a

ae

|

BSSSS8

GUA

282388

BA

Ualee

miwteytm)

wm

wCiejtr)

DSM

mmMMng

je)

MAD

OMB

was

(wes)

(a)

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fa}

(ace)

8)

(ea)

Come)

OZ-9600

IT

TQ-9200

1.

OZ-9600II,

1Q-9200

SYSTEM

CONFIGURATION

Data

Transfer

Cable

CE-315L

OZ/1Q-8000

Series

OZ/AQ-7000

Series

YO-600,

ZQ-6000

Series

ZQ-5000

Series

Computer

PC

Modem

CE-350X

ate

Wireless

Interface

(for

printer)

CE-IR1

CE-IR2

2.

HARD

WARE

DESCRIPTION

1.

Block

diagram

Cee

ee

ee

ee

eee

ee

driver

System

bus

=e.

Application

IC

Card

for

OZ/IQ

series

Except

for

OZ/1Q-709A

OZ/NQ-721

ijmane

AC

Adaptor

OZ/1Q-8B02

(EA-11E)

converter

eee

ee

er

om)

Tablet

eeetetetetetee

<<

%

.¢,

£55054

>

Oo

Q

°

3

<

a

a

SOL

ESRP

(CPU)

KO15-0

KI7-0

ere

Ur

3.072MHz

:

RTC

Ew

Outside

outlet

circuit

electric

.

outlet

a

battery

-ss-

CR-2032

-Memory

‘3

backup

battery

CERAM

1-2

User

reset

Battery

cover

Card

lock

SW

Switch

block

Fig.

1

-3-

OZ-9600

IT

IQ-9200

2.

Description

of

LSI

2-1.

CPU

(LH58061M)

1)

Introduction

@

CMOS

process

@®

8-bit

CPU

(operand

at

8

bits)

@

Firmware

ROM

(decoder)

@

240

bytes

RAM

®

WO

port

(Input)

Key

input

System

control

input

CMT

input

UART

input

General

purpose

input

port

Key

output

Address

output

Chi

enable

output

LCD

driver

control

output

Memory

control

output

(Output)

2)

Block

diagram

wadoosa

yaauo-

Sub-clock

output

CMT

output

UART

output

General

purpose

output

port

Data

input/output

Power

supply

line

Oscillator

line

(input/output)

(Others)

;

©

Internal

circuit

Oscillator

circuitMain,

subsidiary

(for

timer)x2

Reset

circuit

:

UART

,

@

Supply

voltage3.8V~6.0V

Operating

temperature

range-5~55°C

@®

Not

the

bit

slice

microprocessor.

No

arithmetic

function

for

data

above

8

bits.

@

No

multiply

instruction

capability.

@

Does

not

contain

ROM

type

internal

memory

ROM.

®

100-pin

TQFP

(flat

plastic

package)

@

No

radiation

protective

design

provided.

°

TXD

-

@D

X4

X3

CEO

-----------

a a

CE

CONTROL

‘|

DIVIDER

suBosc

|:

INTERRUPT

CONTROL

YSdIAId

LI

RESET

TEST

ON

LHCTRL

Cl

CO

(240Byte)

43aqoo3a

yaauo-d

ees

py

-ORDER

DECODER

REGISTER

CONTROL

REGISTER

\S

Fee

p-ORDER

DECODER

m

MRQ

WR

REGISTER

|

CONTROL

JOYLNOO

ASIGOW

SSSYUGdV

LJ

voD

DIOO

----

DIO7

GND

Fig.2

LH5806AM

block

diagram

TOULNOO

UNVE

uasung

ssaucay

Y3445N@

LHOd-3

x

x

x

a

POWMOAAH

«x

«OK

PES

CJA20

3)

Pin

layout

582

Qqag2

WR

H

H

!

Reset

input

(PD)

OZ-9600

II

IQ-9200

4)

Pin

assignment

RSPR

eyet

.

CPU

signal

Circuit

signal

;

;

Pao,

|

name

|

name

|

YO

|

ALOFF

7~27

A0-A20

A0-A20

fe)

|

28.29

|

CEO.CE1

EXCED,CEIN

|__O

H

p85

ce?

cer

|

[Card

ROM

select,

system

ROM

select

|

p88

eS

CES

Card

RAMselect2

pe

Oe

ll

=

BS

OER

pO.

tM

a

ee

gies

cd

Ma

ROMOR:

ea

a

es

ps2

ee

tc

JPeripheral

vO

select

oo

88

ORS

=

CES

On

A

ee

RAM

OGD

es

|

p87

PD

control

clock,

4oKHz

|

39,40

|

x8,

x4

|

XR

X4

OT

OT

[CT

Forsub-logicosciliation

[|

CH

[Keyinputsignal

(PD)

|

__49~64

|

KOO-KOIS

|

KOO-KOIS

|

O_

|

L

a

ee

ee

or

he

re

hoor

EEO.

=

wy

=

PERO

|

Oro

cbt

de

oe

he

kl

oh

jo

OO

BED

NG

0

eh

ee

Noted

poe

Ofte

2

|e

EE

=

NO

ee

Ms

INetee

=

p68

TEST

ta

|

[ECD

timingsignal,

MHz

peo

ON

ON

Okey

input

interrupt

fo

TxD

TsO

oT

sorr

fT

SOFT

TH

iSpinsenddata

Pmt

tS

pinrecevedata

p72

|

EO

SELECT

|

O__|

Notpredictable

[Notpredictable["

“SOFT

|

H_

[ForiSpin

poo

ES

A

Ne

ee

NOR

p74

ER

S20

_[

Notpredictable

|

Notpredictable

|

SOFT

|

_H__|Cardrecognition

strobe

output

|

75

|

ES

|

ROMBANK

|

O__[

Notpredictable

|

Notpredictable|

SOFT

|

=H

[ROMbankmain

pe

TAT

tRMO

TT

Tittertupt

signalirom

ATC

77

ES

TBINT

-—-}

|_|

fee

ee

ag

78

E6

UNLOCK

PC

Lock

switch

interruptsignal

PO

Et

=

NU

ee

ee

[Not

ap

__E8

RS

—

SOFT

Not

predictable

81

EQ

ER

SOFT

Notpredictable[

SOFT

|

H_[Fori5pin,

82

E10

cD

bot

in

et

eee

Se

ODIO

<=

ae

=

oe

pe

83

E11

DR

fe

ee

eee

hee

OPIN

ee

E12

cTs

fic

a

es

PROS

DID

oe

gn

a

ened

85

E13

Bello

of

tf

|

CTC

tS

pinstartupinput

E14

NU

ee

ae

re

SOFT

|

Notpredictable|"

SOFT

[

H

[Cardoutputenable

[|

CC*dT:

Ss

Forsystemclock

oscillation

For

LCD

control

(not

used)

Test

pin

(GND

connected)

Card

recognition

external

PD

Beeper

output

signal

Memory

1/O

write

pulse

Memory

request

(not.

used)

:

i

xy

c-yx

Reference

voltage

No

backup

power

supply,

VCC

OZ-9600

IT

TQ-9200

2-2.

LCD

driver

(LH1552F,

LH1553F)

1)

Introduction

The

LCD

driver

consists

of

six

segment

driver

(LH1552F)

and

a

com-

mon

driver

(LH1553F).

The

common

driver

has

240

internal

driver

circuits

and

operates

under

the

display

duty

of

1/240,

The

segment

driver

has

168

internal

driver

circuits.

To

abate

the

CPU

load,

connection

is

made

only

to

the

common

driver,

and

the

common

driver

transfers

data

with

a

several

(8

maxi-

mum)

segment

drivers.

The

8-bit

display

data

received

from

the

CPU

are

sent

to

the

common

driver,

and

sent

the

segment

display

RAM

"after

completing

processing

within

the

common

driver.

Common

driver

Maximum

®

Instructions

@

Window

function:

Allows

to

setup

a

maximum

16

windows.

@®

Data

block

transfer

function:

Used

to

write

continuing

data

and

to

send

data

blocks.

@®

Four

rules

of

arithmetic

operation:

Four

rules

of

arithmetic

opera-

tion

of

write

data

with

LCD

display

data

(loop

instruction),

SET,

AND,

OR,

EXOR,

and

NOT

operation

(inverse).

@

Masking:

Masks

the

write

and

read

data.

©

Automatic

address

increment

and

decrement

functions:

Can

inde-

pendently

increment

or

decrement

1

to

8

automatically

towards

direction

X

or

Y

after

accessing

the

write

or

read

address.

©

Vertical

write

and

horizontal

write:

Data

may

be

accessed

vertical-

ly

or

horizontally.

For

vertical

direction,

the

MSB

is

for

8

bits

on

a

column.

For

horizontal

direction,

the

MSP

is

for

8

bits

on

a

row.

8bit

MSB

MSB

8bit

@

Internal

droop

circuit:

To

prevent

a

drooping

phenomenon,

the

FRM

frequency

can

be

varied.

Address

conversion

feature:

When

an

absolute

address

is

ac-

cessed

by

the

CPU,

the

common

driver

distinguishes

to

which

segment

driver

to

be

addressed,

and

converts

it

to

the

absolute

address

for

accessing.

Common

driver

©

Common

output

impedance:

3.0KQ,

maximum.

©

Internal

common

LCD

display

drive

circuit:

240

circuits.

©

Window

RAM

capacity:

688

bits.

©

Segment

driver

Segment

output

impedance:

3.0KQ,

maximum.

o

°

°

°

°

°

Direct

display

of

RAM

data

by

the

internal

display

RM

Data

high:

Bit

active

Data

low:

Bit

inactive

Display

RAM

capacity:

240

x

168

=

40320

bits

(5040

bytes)

Internal

segment

LCD

display

drive

circuit:

168

circuits

Display

duty:

1/240

©

CMOS

process

©

Power

supply

GND

=

0VVec

(logic)

=

3.8V~6.5V

VEE

(LCD)

=

10.0~30.0v

©

PKG

Segment:

217

pins,

tab

film

Common:

325

pins,

tab

film

2)

Block

diagram

(LH1552F

segment

driver)

Supplied

from

the

common

driver

RAM

240

x

168

BITS

oO

uu

Qa

8

uu

Qa

>

v1

v2,V3,v4

04+}

I

Supplied

from

ou

deke

ooseetaeosas

ee

68

LVC.

Fig.4

LH1552F

block

diagram

OZ-9600

IQ-9200

3)

Block

diagram

(LH1553F

common

driver)

é

sau

if

Pee

:

upplied

to

the

seg

river.

X2

Xt

XC2

XCi

LCK1,

LCK2

Hasitest

i

cserset

secs

H240

FRM

MEMORY

a

CONTROL

Timing

UNIT

generator

a

oscillator

[-—

Osc

Control

unit

Supplied

Contrast

;

from

adjust

latch

PROCESSING

.

ee

LVC.

UNIT

r

BUFFER

VR1~8

vcc

RW

DIS

BUSY:

AD

DIO

;

GND

|

CE

CE2

Supplied

tothe

CEB

segment

driver

Fig.5

LH1553F

block

diagram

4)

Common

driver

(LH1553F)

pin

description

V2

ve

Display

drive

power

supply

v1

PGND2

|

xC1

utput

XC2

Input

LCD

clock

GND3__

[GND

TEST?

ley

TESTI

Stpin

Display

off

control

output

FRM

LRW

Segment

data

read/write

signal

(segment

to

segment)

LCK1

:

LOKe

Display

clock

CPU

to

data

bus

input/output

CPU

to

address

bus

input

CE1

CPU

chip

enable

signal

CE2

CE1

and

CE2:

Active

high

CEB

CEB,

Active

low

BUSY

Busy

signal

output

CPU

read/write

signal

cr

m

fe)

Segment

local

chip

enable

output

(for

segment)

Contrast

preset

(with

LVC)

These

8

bits

data

determine

the

LVC

LCD

drive

voltage.

STB

A

high

on

STB

shorts

between

LCD

drive

voltage

VEE

and

GND

using

3K

resistor.

Logic

power

supply

x1

Output

;

X41

Input

Lock

clock

:

X2

ane

Segment

to

segment

local

data

bus:

Output

:

Segment

to

segment

local

address

AY3

LCD

screen

display

address

(absolute),

direction

Y

AX3

AX2

Segment

to

segment

local

address

LCD

screen

display

address

(absolute),

direction

X

OZ-9600IT

TQ-9200

5)

Segment

drive

(LH1552F)

pin

description

-

6)

LCD

driver

waveforms

Signal

+4.

a

vE

8

20~28V

1~168

|

S1~S168

[Segment

output

VO:

oe

peters

;

Display

GND

V4---++

Lope

sess

eee

eee

eee

ee

—

Segment

waveform

ee

Common

waveform

et

SnD

FRM=1

FRM=0

wy

Display

drive

power

supply

SEGMENT

175

VEE

_ |

Display

drive

power

supply

GND

Logic

drive

power

supply

Common

to

common

local

address

179

AX1

180

AX2

LCD

screen

display

address

181

AX3

|

Direction

X

(absolute)

182

AX4

183

AYO

Common

to

common

local

address

COMMON

Input

|

FRM

|

Level

184

AY1

1

1

v2

185

AY2

LCD

screen

display

address

0

1

V6

186

AY3

Direction

Y

(absolute)

1

0

Vi

187

AY4

188

AY5

: 2

ve

189

AY6

190

AY7

191

LDI07

[Common

to

common

local

data

bus

192

LDIO6

=|

input/output

2-3.

RTC

(SMC5245)

193

LDIO5

.

194

LDIO4

1)

Pin

layout

195

LDIO3

eke

BES

eng

nN

=

MUO

uy

Wu

rs

uw

use

ae

SOR

CELSS

ESSE

LCE

200

LCK1

201

LCK2

Segment

data

read/write

signal

(common

to

LRW

common)

:

Frame

signal

DIS

Display

off

control

input

MIRROR

|

Mirror

reflect

input

206

TEST1

207

|

TEST2

|Testpin

208

GND

|GND

iad

ancl

209

VCC

__

|Logic

drive

power

supply

GND

|GND

;

Display

drive

power

supply

Local

to

local,

local

chip

enable

input

Display

clock

(common

to

common)

Display

drive

power

supply

isp]

onrN

BHEaARBE

>Hooo

a

Fig.6

SMC5245

pin

layout

Display

drive

power

supply

GND

2)

Pin

description

Function

RW

NC

AO

At

A2

A3

A4

Do

DI

D2

D3

D4

D5

NC

D6

D7:

ALARM

INSRES

VDETO

.

SRES

ON

OCE2

OCE1

OCEO

SCE

NC

BTCOV

RSKEY

ONKEY

ICE2

VSS

—

o0o0o0o000

0-0

Supply

voltage

Not

used.

Not

used.

|

Reset

terminal

Crystal

oscillator

connect

pin

.

Crystal

oscillator

connect

pin

‘|

Not

used.

Internal

low

voltage

output

regulation

capacity

connect

pin

Frequency

output

pin

Voltage

monitor

pin

Voltage

monitor

pin

Voltage

monitor

pin

Voltage

monitor

pin

Test

pin

Chip

select

pin

Chip

select

pin

Chip

select

pin

Read/write

pin

Not

used.

Address

bus

Address

bus

Address

bus

Address

bus

Address

bus

Data

bus

Data

bus

Data

bus

Data

bus

Data

bus

Data

bus

Not

used.

Data

bus

Data

bus

Interrupt

output

pin

Reset

input

pin

VDD

output

monitor

pin

Reset

output

pin

ON

key

output

pin

WR

output

pin

|

‘Not

used.

Not

used.

©

D

battery

protection

control

pin

Not

used.

Battery

replace

pin

Reset

switch

|

ON

key

input

pin

WR

input

pin

Power

supply

OZ-9600

II

IQ-9200

3)

Introduction

The

SMC5245

is

a

calendar

combined

real

time

clock.

It

has

a

basic

frequency

of

32,768Hz

generated

from

a

crystal

oscillator

to

produce

second,

minute,

hour,

day,

day

of

week,

month,

and

year.

It

has

an

automatic

leap

year

interrogating

feature

of

the

world

calendar,

cyclic

interrupt

feature,

2-channel

alarm

feature,

and

a

4-channel

external

voltage

detect

feature.

For

interfacing

with

a

microcomputer,

it

uses

8-bit

data

bus,

5-bit

address

bus,

3-bit

chip

select

and

read/write

signals,

allowing

to

set

time,

alarm,

interrupt

and

to

read

time,

interrupt

cause,

and

voltage

detect

result.

A

part

of

the

oscillation

circuit

and

the

frequency

divider

are

driven

by

a

low

voltage

for

a

low

power

consumption.

4)

Features

@

High

speed

CPU

interface

by

means

of

8-bit

data

bus.

*

©

Internal

time

counter

(second,

minute,

hour)

and

calendar

(day,

day

of

week,

month,

year).

®

internal

automatic

leap

year

recognition

feature

@

internal

2-channel

alarm

feature

with

a

wild

card

feature

©

Internal

cyclic

interrupt

feature

(day,

hour,

minute,

second,

1/2

second)

©

Internal

4-channel

external

voltage

detect

circuit

@

Low

power

dissipation

using

the

CMOS

technology

and

the

volt-

age

regulator

Internal

32.768Hz

crystal

oscillator

5)

Pin

functions

@

D0~D7:

8-bit

data

bus

These

are

bidirectional

data

bus

that

connected

with

the

microcomputer

data

bus

and

used

to

read/write

counters

and

registers.

The

data

bus

is

at

a

high

impedance

except

when

CS0~CS2

is

active

and

R/W

is

at

a

high.

@

A0~A4:

5-bit

address

bus

These

are

address

input

lines

that

are

within

the

microcomputer

address

bus

and

used

to

assign

read/write

counters

and

registers.

@

CS0~CSS5:

5-bit

address

bus

These

are

chip

select

lines

used

to

set

active

and

inactive

the

IC.

Normally,

address

decoded

signal

is

connected.

CSO

is

an

active

low

signal.

CS1

and

CS2

are

active

high

or

low

that

can

be

selected

by

masking.

The

IC

becomes

active

when

the

3-bit

select

line

has

turned

active.

®

Read/Write

pin

The

contents

of

the

counter

and

the

register

designated

in

ad-

dress

AO~A4

at

HIGH

level

are

outputted

to

the

data

bus.

Writing

is

performed’

at

LOW

level.

When

CS0~CS2

are

non-active,

neither

read

nor

write

can

be

made.

©

ALARM

interrupt

output

pin

—

Cyclic

interrupt,

alarm

interrupt,

and

voltage

detect

interrupt

are

informed

to

the

external

source.

With

a

mask

option,

active

low

or

high

state

can

be

selected.

Only

the

software

can

be

assigned

to

set

this

line

for

set

active

or

anaenve:

These

lines

are

not

affected

by

CS0~CS2.

©

FOUR

frequency

output

pin

The

frequency

of

32Hz

is

sent

onto

this

output

line

for

step

adjust-

ment

of

the

clock.

@

OSC1,

OSCO

crystal

oscillator

connect

pin

These

are

pins

connected

with

the

32,768

crystal

oscillator.

®

VDO0~VD3

detect

voltage

pin

These

are

input

lines

used

to

monitor

external

voltage.

@

Pin

numbers

2,

3,

35~48

(QFP,

48

pins)

user

circuit

i/o

pins

input/output

pins

used

for

the

user

circuit.

@

VDD,

VSS

power

supply

pin

These

lines

are

used

to

supply

power.

@

VREG

internal

low

voltage

output

regulation

capacitor

connect

pin

A

0.1

capacitor

is

connected

across

VREG

and

VSS.

OZ-9600

IT

TQ-9200

@®

RESET

reset

pin

This

line

is

used

to

initialize

the

IC.

A

high

on

this

line

initializes

all

register

contents.

In

addition

to

this

function,

it

also

has

an

internal

power-on-reset

circuit.

The

reset

is

OR’ed

with

the

power-on-reset

circuit.

Internal

pulldown

is

not

provided

on

the

reset

line.

NOTE:

The

power-on-reset

circuit

may

not

start

active

depending

on

how

the

power

is

turned

on.

@®

TEST

test

pin

Only

Seiko

Epson

may

provide

it

for

test

of

the

IC.

Normally,

it

is

internally

pulled

down.

It

is

suggested

to

connect

with

VSS

exter-

nally.

6)

User

circuit

The

user

circuit

consists

of

14

input/output

lines.

ONKEY,

RSKEY,

and

BTCOV

lines

are

Schmitt

trigger

inputs

that

normally

pulled

down

internally.

The

one-shot

circuit

issues

a

high

level

signal

(normally

low)

to

the

8/512~9/512

one-shot

circuit

at

a

high

to

low

transition

of

the

BTCOV

line.

The

one-shot

circuit

has

a

trigger.

The

one-shot

circuit

output-2

has

a

delay

of

1/2024~3.1024

second

and

continues

to

sent

high

level

until

the

BTCOV

line

becomes

high

(normally

low).

The

VDA

signal

is

an

output

from

the

voltage

detector

A.

A

high

level

signal

is

issued

when

normal

(voltage

found).

This

signal

is

at

a

high

at

a

time

of

initialization.

The

NADOCW

signal

is

an

active

low

ad-

dress

0CH

write

signal.

The

DFR

signal

is

a

register

of

a

user

bit

that

sends

the

input

level

of

D

to

Q

at

a

low

to

high

transition

of

signal.

When

a

low

level

signal

is

received

by

R,

the

DFR

is

reset

with

a

low

level

signal

sent

to

Q.

(XQ

is

an

invert

output

of

Q).

0G

NADOCH

INSRES

7

ake

2212

VDA

eee

{>

7

ICEO

faq)

ze

Pipst

1CEA

21

Ay

7

3iN2

Se

>

2nc4

1

1.—3

1

Ice

1

22%

—~o2

2)

TR

o22,

St?

1.—3

we

ONKEY

oe

Ij)

1S

e

13

3

RSKEY

241

2]

)

;

Be:

tho!

ee

‘

ae

2

i)

4

BTCOV

2

fo

22

ie

onesHor

|

2-4.

System

gate

array

(LZ95G33)

1)

Brief

functional

description

@

Memory

decode

‘

Used

to

decode

the

system

ROM,

RAM,

and

IC

card

memories

that

produces

a

chip

select

signal

for

each

assigned

device.

@

Write

pad

interface

Has

an

interface

circuitry

with

the

handwrite

pad.

@

Optical

communication

interface

Not

only

switches

the

CPU

serial

port

to

a

normal

15-pin

port

from

the

optical

communication,

it

also

modules

the

optical

communica-

tion.

;

@

CDROM

interface

Not

only

switches

the

normal

serial

port

from

the

CDROM,

it

also

switches

the

CDROM

drive,

and

it

controls

the

communication

with

the

CDROM

drive.

©

Tablet

conirol

Used

to

control

the

tablet

input

and

the’

A/D

converter.

©

Memory

protect

The

memory

is

protected

using

an

external

voltage

detect

IC.

OCE1

SRES

VDETO

-10-

@

EEPROM

control

Used.

to

control

the

EEPROM

access,

and

has

a-function

to

replace

a

part

of

ROM

to

a

part

of

the

EEPROM.

Used

to

generate

clocks

and

low

battery

signal

cut

out

function.