Intel Pentium II Installation and operating instructions

Pentium

Processor –

Low-Power Module at 266 MHz

Memory Bus Simulation

Methodology

Application Note

June 1999

Order Number: 273217-002

Application Note

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future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Pentium®II processor – Low-Power Module may contain design defects or errors known as errata which may cause the products to deviate from

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Application Note 3

Low-Power Module Memory Bus Simulation Methodology

Contents

1.0 Introduction..................................................................................................................5

1.1 Key Terms.............................................................................................................5

1.2 Related Documents...............................................................................................5

2.0 SimulationPrerequisites.........................................................................................6

3.0 SimulationBlockDiagram......................................................................................6

4.0 Details of the Electrical Interconnect Models.................................................7

5.0Simulation Conditions..............................................................................................8

6.0 Flight Time andSignal QualityDefinitions....................................................11

6.1 Procedure 1:Determining Flight Time.................................................................11

6.1.1Flight Time Determinationfor Setup Time..............................................12

6.1.2Hold Time...............................................................................................13

6.2 Procedure 2:Signal Quality.................................................................................14

Figures

1Simulation Model Components.............................................................................7

2400-pin Connector Package Model.......................................................................8

3DIMM Connector Package Model.........................................................................8

4DIMM Connection..................................................................................................9

5Determining Flight Time......................................................................................11

6Flight Time (Rising Edge)....................................................................................12

7Flight Time (Falling Edge)...................................................................................13

8Flight Time Measurement (With Ringing)............................................................15

Tables

1Related Intel Documents.......................................................................................5

2Fast, Slow, and Worst-Case Signal Quality Corner InterconnectModels.............7

3Low-Power Module Memory Interface Pin Loading...............................................9

4Simulation Conditions..........................................................................................10

5Signal Quality Criteria..........................................................................................14

Low-Power Module Memory Bus Simulation Methodology

Application Note 5

1.0 Introduction

This application note describes a simulation methodology for interfacing memory signals from the

Intel® Pentium®II Processor – Low-Power Module to the 66-MHz Unbuffered SDRAM Dual In-

Line Memory Modules (SDRAM DIMM).

The models used to drive the simulation tool are based on the I/O Buffer Industry Standard (IBIS).

1.1 Key Terms

The Low-Power Module is identical to the Pentium II Processor Mobile Module Connector

(MMC-2). A complete description of this module is located in the Intel

Pentium

II Processor –

Low-Power Module datasheet (order number 273256).

Intel 440BX AGPset refers to both the 82443 BX Host Bridge/Controller and the 82371EB PCI

ISA IDE Xcelerator. A complete description of this chipset is located in both the Intel

440BX

AGPset: 82443BX Host Bridge/Controller datasheet (order number 290633) and the 82371AB

PCI-TO-ISA/IDE Xcelerator (PIIX4) datasheet (order number 290562).

SDRAM DIMM refers to synchronous DRAM dual in-line memory modules.

SE Board refers to the system electronics board.

1.2 Related Documents

These documents are available for download from Intel’s World Wide Web site at

http://www.intel.com.

Table 1. Related Intel Documents

Document Order Number

Intel

Pentium

Processor – Low-Power Module

datasheet 273256

Mobile Pentium

Processor Specification Update

243887

82371AB PCI-TO-ISA/IDE Xcelerator (PIIX4)

datasheet 290562

Intel

440BX AGPset: 82443BX Host Bridge/Controller

datasheet 290633

82443BX Host Bridge/Controller Electrical and Thermal Timing Specification

datasheet addendum

273218

Intel

440BX AGPset: 82443BX Host Bridge/Controller Specification Update

290639

Low-Power Module Memory Bus Simulation Methodology

6Application Note

2.0 Simulation Prerequisites

The following information is needed to simulate the Low-Power Module memory bus:

•Pentium

II Processor Mobile Module MMC-2 I/O Buffer Model Specification, Rev 1.0

(contact your Intel Field Sales Representative)

— Module interconnect specifications

— Connector parameters

•82443BX Electrical and Thermal Timing Specifications datasheet addendum, Rev 1.0

(order number: 273218)

— 82443BX AC and DC Specifications

•4-Clock 66 MHz 72-Bit ECC Unbuffered SDRAM DIMM Design Specification, Rev 1.0

(http://developer.intel.com/)

— DIMM board layout

— SDRAM AC and DC specifications

•I/O Buffer Models

— 82443BX IBIS model, Rev 1.2 (contact your Intel Field Sales Representative). The

82443BX IBIS model is used for the Intel®440BX AGPset chipset.

— SDRAM component IBIS models. The 66-MHz unbuffered SDRAM IBIS models are

available in x8 and x16 configurations from various memory manufacturers.

3.0 Simulation Block Diagram

Figure 1 shows the simulation block diagram for the Low-Power Module/DIMM memory

interface. The Pentium II Processor Mobile Module MMC-2 I/O Buffer Model describes the

interconnect characteristics between the Low-Power Module 400-pin connector, and the 82443BX

Host Bridge/Controller.

As shown in Figure 1, the 400-pin connector is used to model the net (TL-1) and the 400-pin

connector model. The 4-clock, 66-MHz, 72-bit Unbuffered SDRAM DIMM specification, which

describes the interconnect characteristics of the SDRAM DIMM, is used to model the nets (TL-3,

TL-4, TL-5, TL-6) of DIMM. Based on all the corners of simulations, as described in Section 5.0,

the interconnect on the system electronics (SE) board (TL-2) can be specified to meet the setup/

hold requirements for both the SDRAM and 82443BX Host Bridge/Controller.

Low-Power Module Memory Bus Simulation Methodology

Application Note 7

4.0 Details of the Electrical Interconnect Models

This section provides detailed information on the electrical interconnect models used for the

simulation. Table 2 lists the assumed characteristics for the Low-Power Module, the SE board, and

the DIMM interface, for fast, slow, and worst-case signal quality models.

Figure 1. Simulation Model Components

A6429-01

TL-4

TL-3TL-2TL-1 TL-5

TL-6

82443BX

IBIS

SDRAM

IBIS

400-pin

Connector DIMM

Connector .

Table 2. Fast, Slow, and Worst-Case Signal Quality Corner Interconnect Models

Component Parameter Fast Typical Slow Units

Low-Power Module

Impedance (Z0)475563Ω

Dielectric (Er)4.14.44.8

Trace Propagation Delay (tpd) 138 162 186 ps/in

SE Board

Impedance (Z0)475563Ω

Dielectric (Er)4.14.44.8

Trace Propagation Delay (tpd) 138 162 186 ps/in

DIMM

Impedance (Z0)607080Ω

Dielectric (Er)4.24.44.8

Trace Propagation Delay (tpd) 133 158 183 ps/in

Low-Power Module Memory Bus Simulation Methodology

8Application Note

Figure 2, shows the Pi-element network model used for the 400-pin module connector.

Figure 3 shows the Pi-element network model used for the DIMM connector.

5.0 Simulation Conditions

The DIMM topology routing for each signal is defined in the 4-Clock 66 MHz 72-Bit ECC

Unbuffered SDRAM DIMM design specification. Figure 4 shows the 2-DIMM system connection

and the possible receiver pin loads for each memory signal. For example, a fully populated x8 with

ECC arrangement for a 2-DIMM system yields the heaviest receiving pin load (2 x 18 = 36 loads)

on the SRAS_A#, SCAS_A#, WE_A#, and MAB# signals, as shown in Table 3. Since the Low-

Power Module is also designed to support a 1-DIMM system, a x16 arrangement DIMM yields the

lightest pin load (four loads) on the same signals.

The heaviest and lightest receiving pin loads for each Low-Power Module memory signal is used

for slow (setup) and fast (hold) corner simulations, respectively.

The DIMMs used for this simulation are x8, x8 with ECC, and x16 DIMM arrangements.

Figure 2. 400-pin Connector Package Model

AA6430-01

R = 0.01 Ohms L = 3.5 nH

C =

0.5 pF C =

0.5 pF

Figure 3. DIMM Connector Package Model

A6431-01

R = 0.027 Ohms L = 5 nH

C =

0.9 pF C =

0.9 pF

Low-Power Module Memory Bus Simulation Methodology

Application Note 9

Figure 4. DIMM Connection

Table 3. Low-Power Module Memory Interface Pin Loading

SDRAM

Signals

Number of Populated

DIMM Sockets on

SE Board†

Number of Pin Loads

DIMM x8 DIMM x8

with ECC DIMM x16

SRAS_A# 1 min, 2 max 8 min, 16 max 9 min, 18 max 4 min, 8 max

SCAS_A# 1 min, 2 max 8 min, 16 max 9 min, 18 max 4 min, 8 max

WE_A# 1 min, 2 max 8 min, 16 max 9 min, 18 max 4 min, 8 max

MAB[x:x]# 1 min, 2 max 8 min, 16 max 9 min, 18 max 4 min, 8 max

CKE[x:x] 1894

CS_A[x:x]# 1894

MD[x:x], MECC[x:x] 1 min, 2 max 1 min, 2 max 1 min, 2 max 1 min, 2 max

DQM_A[x:x]# 1 min, 2 max 1 min, 2 max 1 min, 2 max 1 min, 2 max

†Assumes a 2-DIMM socket system.

DIMM 1

DIMM 0

Closest Connector

Farthest Connector

CS_A[3:2]#, CS_A[3:2]#

CS_A[1:0]#, CS_A[1:0]#

WE_A#

SRAS_A#

SCAS_A#

DQM_A[7:0]#

MECC[7:0]

MD[63:0]

DIMM_CLK[3:0]

DIMM_CLK[7:4]

SMB_CLK

SMB_DATA

CKE_[1:0]

CKE_[3:2]

RAS

CAS

/S1/S0,/S3/S2

DQ[63:0]

CB[7:0]

DQM

CK[3:0]

CKE

SCL

SDA

MAB[12:11,9:0]#, MAB[13,10] A[13:0]

Low-Power Module Memory Bus Simulation Methodology

10 Application Note

Table 4 lists the Low-Power Module/DIMM condition used in the simulation. Each driver/receiver

pair of the memory signal with the heaviest/lightest pin load is simulated with these conditions.

The first four entries of the table are used for slow corner (setup) simulations in conjunction with

heaviest receiver pin loads of the driver/receiver signal pair. The last four entries of the table are

used for fast corner (hold) and signal quality simulations in conjunction with the lightest receiver

pin loads of the driver/receiver signal pair.

In general, a simulation tool assumes a no-loss transmission line in the pre-layout simulation. Also,

each signal is simulated as a single net. No crosstalk is taken into account.

After the S.E. board is designed to meet the memory interface trace length requirement, a crosstalk

simulation can be run with two adjacent parallel lines. The stackup and trace width are varied to

run a fast and slow corner simulation. However, this document only describes the methodology for

pre-layout simulations.

Table 4. Simulation Conditions

Driver Receiver

Low-Power

Module/SE Board

Trace Velocity

(ns/in)

DIMM

Trace Velocity

(ns/in)

Low-Power

Module/SE Board

Impedance

(ohms)

DIMM

Impedance

(ohms)

Slow Slow 0.186 0.183 63 80

Slow Slow 0.186 0.183 63 60

Slow Slow 0.186 0.183 47 80

Slow Slow 0.186 0.183 47 60

Fast Fast 0.138 0.133 63 80

Fast Fast 0.138 0.133 63 60

Fast Fast 0.138 0.133 47 80

Fast Fast 0.138 0.133 47 60

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