Efinix Titanium User manual
Titanium Interfaces
User Guide
UG-TiINTF-v2.0
February 2022
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Copyright © 2022. All rights reserved. Efinix, the Efinix logo, the Titanium logo, Quantum, Trion, and Efinity are trademarks of Efinix, Inc. All other
trademarks and service marks are the property of their respective owners. All specifications subject to change without notice.
Titanium Interfaces User Guide
Contents
About the Interface Designer.........................................................................................................iv
Chapter1:Get Oriented.................................................................................................................. 5
Interface Blocks..........................................................................................................................................7
Package/Interface Support Matrix...........................................................................................................8
Interface Block Connectivity.................................................................................................................... 8
Designing an Interface............................................................................................................................. 9
Create or Delete a Block....................................................................................................................... 10
Using the Resource Assigner................................................................................................................ 11
Resource View..............................................................................................................................12
Importing and Exporting Assignments.....................................................................................13
Interface Designer Output Files............................................................................................................15
Scripting an Interface Design................................................................................................................15
Chapter2:Device Settings............................................................................................................17
Configuration Interface...........................................................................................................................17
Enable Internal Configuration....................................................................................................17
About SEU Detection.................................................................................................................. 17
Enable SEU Detection.................................................................................................................18
SEU Detection Circuitry.............................................................................................................. 19
Design Check: Configuration Messages............................................................................................. 20
I/O Banks Interface................................................................................................................................. 21
Titanium I/O Banks................................................................................................................................. 21
Dynamic Voltage Support......................................................................................................................22
Design Check: I/O Bank Messages......................................................................................................23
Chapter3:Clock and Control Networks....................................................................................... 24
Clock Sources that Drive the Global and Regional Networks.......................................................... 26
Configuring the Dynamic Clock Multiplexers..................................................................................... 27
Driving both the Global and Regional Networks............................................................................... 27
Design Check: Clock Control Messages............................................................................................. 28
Chapter4:DDR Interface.............................................................................................................. 31
About the DDR DRAM Interface............................................................................................................ 31
DDR Interface Designer Settings.......................................................................................................... 37
Chapter5:GPIO Interface............................................................................................................. 39
Types of GPIO...........................................................................................................................................39
Features for HVIO and HSIO Configured as GPIO.............................................................................41
Double-Data I/O.......................................................................................................................... 42
Programmable Delay Chains..................................................................................................... 43
About the HVIO Interface....................................................................................................................... 44
About the HSIO Interface....................................................................................................................... 46
HSIO Configured as GPIO.....................................................................................................................47
Using the GPIO Block.............................................................................................................................50
Using the GPIO Bus Block..................................................................................................................... 53
Create a TX Serializer Interface............................................................................................................ 54
Create a RX Deserializer Interface........................................................................................................55
Design Check: GPIO Messages............................................................................................................ 56
Chapter6:LVDS Interface............................................................................................................. 67
HSIO Configured as LVDS..................................................................................................................... 67
Using the LVDS Block.............................................................................................................................73
Create an LVDS TX Interface................................................................................................................. 75
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Titanium Interfaces User Guide
Create an LVDS RX Interface.................................................................................................................77
Design Check: LVDS Errors and Warnings..........................................................................................78
Chapter7:HyperRAM Interface.................................................................................................... 86
About the HyperRAM..............................................................................................................................86
Using the HyperRAM Interface............................................................................................................. 87
Chapter8:JTAG User TAP Interface............................................................................................. 89
JTAG Mode.............................................................................................................................................. 89
Using the JTAG User TAP Block........................................................................................................... 92
Design Check: JTAG User Tap Errors and Warnings.........................................................................93
Chapter9:MIPI RX/TX Lane Interface.......................................................................................... 94
HSIO Configured as MIPI Lane...............................................................................................................94
MIPI Groups by Package........................................................................................................................99
Using the MIPI TX Lane or MIPI RX Lane Block................................................................................103
Create a MIPI TX Interface...................................................................................................................104
Create a MIPI RX Interface.................................................................................................................. 106
Design Check: MIPI Lane Messages.................................................................................................. 107
Chapter10:MIPI D-PHY Interface...............................................................................................110
MIPI RX D-PHY.......................................................................................................................................110
MIPI TX D-PHY.......................................................................................................................................113
MIPI DPHY TX Interface Designer Settings....................................................................................... 117
MIPI DPHY RX Interface Designer Settings.......................................................................................119
Chapter11:PLL........................................................................................................................... 121
About the PLL Interface........................................................................................................................ 121
Using the PLL V3 Block........................................................................................................................123
Using the PLL Clock Calculator...............................................................................................123
Understanding PLL Phase Shifting..........................................................................................124
Manually Configuring the PLL................................................................................................. 124
Implementing a Zero-Delay Buffer.....................................................................................................125
Design Check: PLL Errors.................................................................................................................... 126
Chapter12:Oscillator................................................................................................................. 131
Using the Oscillator Block................................................................................................................... 131
Design Check: Oscillator Errors......................................................................................................... 131
Chapter13:SPI Flash Interface...................................................................................................133
About the SPI Flash Memory...............................................................................................................133
Using the SPI Flash Interface.............................................................................................................. 134
Chapter14:Interface Floorplans................................................................................................ 135
Icon Reference.............................................................................................................................137
Revision History.......................................................................................................................... 138
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Titanium Interfaces User Guide
About the Interface Designer
Titanium FPGAs wrap a Quantum™-accelerated core with a periphery that sends signals
out to the device pins. The core contains the logic, embedded memory, and multipliers. The
device periphery includes blocks such as GPIO pins, LVDS, MIPI, DDR, and PLLs.
The tools in the Efinity® main window help you design the logic portion of your design. You
use the Efinity Interface Designer to build the peripheral portion of your design.
Figure 1: Conceptual View of Interface Blocks
Embedded Memory
Multiplier
Note: The number and locations of blocks
are shown for illustration purposes only.
The actual number and position depends
on the device.
Interface Blocks:
Use the Efinity Interface Designer to create and
define these blocks and to connect them to
your RTL design via the signal interface.
Programmable Core Fabric:
Create your RTL design for the core fabric
using Efinity design tools.
Signal Interface:
Connects the core fabric to the interface blocks
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Titanium Interfaces User Guide
Chapter 1
Get Oriented
Contents:
•Interface Blocks
•Package/Interface Support Matrix
•Interface Block Connectivity
•Designing an Interface
•Create or Delete a Block
•Using the Resource Assigner
•Interface Designer Output Files
•Scripting an Interface Design
The Interface Designer has four main sections:
•Design Explorer—Provides a list view of the interface blocks you have in your design
organized by block type. It also includes device-wide settings for the I/O banks and
configuration options. Select a block to display it's summary and editor.
•Block Summary—Displays the current settings for the selected block.
•Block Editor—Provides options and settings for the selected block. The editor may have
more than one tab, depending on the block.
•Resource Assigner—Provides an easy, tabular method for assigning resources. View by
instance (default) or resource.
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Titanium Interfaces User Guide
Figure 2: Interface Designer
When you first open the Interface Designer for your project, the Design Explorer shows the
Device Settings folder (with default settings) and empty folders for the interface blocks your
chosen device supports. You need to add blocks as required for your design.
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Titanium Interfaces User Guide
Interface Blocks
Titanium FPGAs support a variety of interface blocks. The available blocks differ depending
on which FPGA you target. You need to assign a resource for every block you use.
The following table describes the interface blocks supported in the Efinity® software version
2021.2.
Table 1: Titanium Interface Blocks
Interface Ti35 Ti60 Ti90 Ti120 Ti180
DDR
GPIO
GPIO bus
I/O bank
JTAG User TAP
LVDS TX
LVDS RX
Bidirectional
LVDS
MIPI DPHY
MIPI TX Lane
MIPI RX Lane
PLL (V3)
Oscillator
All interface blocks have an instance name that must be a unique identifier. When you add
a new block, the Interface Designer gives the block a unique default name, which you can
change.
Note: Many fields in the Block Editor allow arbitrary names. After you type a new name, press Enter or
click Save to save the name.
Pin names are the top-level ports of the design implemented in the core that connect to the
interface block. These names must be legal Verilog HDL or VHDL identifiers.
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Titanium Interfaces User Guide
Package/Interface Support Matrix
Some interfaces are only available in certain packages. The following table describes which
interfaces are supported in specific FPGA/package combinations for the Efinity® software
v2021.2.
Table 2: Titanium Interface/Package Combinations Supported in Efinity® Software
v2021.2
Package Ti35 Ti60 Ti90, Ti120, Ti180
W64
F100
F225
M484
Titanium Family Legend:
Oscillator PLL LVDS MIPI RX or
TX Lane
MIPI D-PHY
Controller
DDR DRAM
Controller
Interface Block Connectivity
The FPGA core fabric connects to the interface blocks through a signal interface. The
interface blocks then connect to the package pins. The core connects to the interface blocks
using three types of signals:
•Input—Input data or clock to the FPGA core
•Output—Output from the FPGA core
•Clock output—Clock signal from the core clock tree
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Titanium Interfaces User Guide
Figure 3: Interface Block and Core Connectivity
FPGA
Signal
Interface
Core
Interface
Block
Input
Output
Clock Output
Interface
Block
GPIO
Input
Output
Clock Output
Interface
Block
Input
Output
Clock Output
Interface
Block
Input
Output
Clock Output
GPIO blocks are a special case because they can operate in several modes. For example, in
alternate mode the GPIO signal can bypass the signal interface and directly feed another
interface block. So a GPIO configured as an alternate input can be used as a PLL reference
clock without going through the signal interface to the core.
When designing for Titanium FPGAs, you create an RTL design for the core and also
configure the interface blocks. From the perspective of the core, outputs from the core are
inputs to the interface block and inputs to the core are outputs from the interface block.
The Efinity netlist always shows signals from the perspective of the core, so some signals do
not appear in the netlist:
•GPIO used as reference clocks are not present in the RTL design, they are only visible in
the interface block configuration of the Efinity® Interface Designer.
•The FPGA clock tree is connected to the interface blocks directly. Therefore, clock
outputs from the core to the interface are not present in the RTL design, they are only
part of the interface configuration (this includes GPIO configured as output clocks).
The following sections describe the different types of interface blocks in the Titanium. Signals
and block diagrams are shown from the perspective of the interface, not the core.
Designing an Interface
Save Check Design Generate Report
Generate Efinity
Constraint Files
Exit
Designing your interface is straightforward: add interface blocks, configure them, and then
generate reports and constraints. The Efinity software uses the constraints during compilation
to connect signals from the core to your interface.
Note: Refer to Create or Delete a Block on page 10 and Interface Blocks on page 7 for instructions on
adding blocks and configuring them.
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Titanium Interfaces User Guide
During the design process, you can generate reports, which are available in the Efinity®
Results tab. When you generate reports, the software also saves your design.
Use the design checker to check the interface for errors and to ensure that your settings are
valid. The Interface designer displays design issues in the message viewer window. You can
also export design issues (Design > Export Design Issues) to generate a comma separated
values (.csv) report to view the issues in a spreadsheet application. When you run the design
checker, the software automatically saves your interface.
When you are done configuring your interface, click the Export Efinity Constraints Files
button to export the interface constraints to your project. The software saves the design,
checks it for errors, generates the interface reports and the interface constraint files.
Click Exit to close the Interface Designer and return to the Efinity® main window.
Note: You can leave the Interface Designer open while running the Efinity® software. However, if you
make changes to the Efinity project, the Interface Designer is not updated until the next time you launch it.
Create or Delete a Block
Create Block Create GPIO Bus Delete Block
To create a block:
1. Select the folder for the block type you want to create.
2. Click the Create Block button.
To create a GPIO bus, click the GPIO folder and then click the Create GPIO Bus button.
To delete a block, select the block name and click the Delete Block button.
Tip: Right-clicking a folder name opens a context-sensitive menu. From there you can choose Create Block (and
Create Bus for GPIO).
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