Cypress CY62138EV30 User manual

2-Mbit (256K x 8) MoBL®Static RAM

CY62138EV30

MoBL®

Cypress Semiconductor Corporation • 198ChampionCourt • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-05577 Rev. *A Revised February 14, 2006

Features

• Very high speed: 45 ns

— Wide voltage range: 2.20V – 3.60V

• Pin-compatible with CY62138CV30

• Ultra-low standby power

—Typical standby current: 1 µA

—Maximum standby current: 7 µA

•Ultra-low active power

— Typical active current: 2 mA @ f = 1 MHz

• Easy memory expansion with CE and OE features

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Offered in Pb-free 36-ball BGA package

Functional Description[1]

The CY62138EV30 is a high-performance CMOS static RAM

organized as 256K words by 8 bits. This device features

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life™ (MoBL®) in

portable applications such as cellular telephones. The device

also has an automatic power-down feature that significantly

reduces power consumption. The device can be put into

standby mode reducing power consumption when deselected

(CE HIGH).

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O

pins (I/O0through I/O7) is then written into the location

specified on the address pins (A0through A18).

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing Write

Enable (WE) HIGH. Under these conditions, the contents of

the memory location specified by the address pins will appear

on the I/O pins.

The eight input/output pins (I/O0through I/O7) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), or during a write

operation (CE LOW and WE LOW).

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Logic Block Diagram

COLUMN

DECODER

ROW DECODER

SENSE AMPS

Data in Drivers

POWER

DOWN

I/O0

I/O1

I/O2

I/O3

256K x 8

ARRAY

I/O7

I/O6

I/O5

I/O4

A12

A13

A14

A15

A16

A10

A11

A17

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MoBL®

Document #: 38-05577 Rev. *A Page 2 of 9

Pin Configuration[2]

Product Portfolio

Product VCC Range (V) Speed

(ns)

Power Dissipation

Operating ICC (mA) Standby ISB2 (µA)f = 1 MHz f = fmax

Min. Typ.[3] Max. Typ.[3] Max. Typ.[3] Max. Typ.[3] Max.

CY62138EV30LL 2.2 3.0 3.6 45 2 2.5 15 20 1 7

Notes:

2. NC pins are not connected on the die.

3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA= 25°C.

A15

VCC

A13

A12

WE A7

I/O4

I/O5

I/O6

I/O7

A11

A10

VSS

I/O0

Vcc

I/O1

I/O2

I/O3

A17

A16

A9A14

Top View

FBGA

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MoBL®

Document #: 38-05577 Rev. *A Page 3 of 9

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature ..................................–65°C to +150°C

Ambient Temperature with

Power Applied...............................................55°C to +125°C

Supply Voltage to Ground

Potential........................................ –0.3V to VCC(MAX) + 0.3V

DC Voltage Applied to Outputs

in High-Z State[4,5]......................... –0.3V to VCC(MAX) + 0.3V

DC Input Voltage[4,5]......................–0.3V to VCC(MAX) + 0.3V

Output Current into Outputs (LOW).............................20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current.....................................................> 200 mA

Product Range Ambient

Temperature VCC[6]

CY62138EV30LL Industrial –40°Cto+85°C 2.2V to

3.6V

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions

CY62138EV30-45

UnitMin. Typ.[3] Max.

VOH Output HIGH Voltage IOH = –0.1

mA VCC = 2.20V 2.0 V

IOH = –1.0

mA VCC = 2.70V 2.4 V

VOL Output LOW Voltage IOL = 0.1 mA VCC = 2.20V 0.4 V

IOL = 2.1 mA VCC = 2.70V 0.4 V

VIH Input HIGH Voltage VCC = 2.2V to 2.7V 1.8 VCC + 0.3V V

VCC= 2.7V to 3.6V 2.2 VCC + 0.3V V

VIL Input LOW Voltage VCC = 2.2V to 2.7V –0.3 0.6 V

VCC= 2.7V to 3.6V –0.3 0.8 V

IIX Input Leakage

Current GND < VI< VCC –1 +1 µA

IOZ Output Leakage

Current GND < VO <VCC,

Output Disabled –1 +1 µA

ICC VCC Operating

Supply Current f = fMAX =

1/tRC VCC = VCCmax

IOUT = 0 mA

CMOS levels

15 20 mA

f = 1 MHz 2 2.5 mA

ISB1 Automatic CE

Power-down

Current — CMOS

Inputs

CE > VCC – 0.2V, VIN >VCC – 0.2V,

VIN <0.2V), f = fMAX (Address and

Data Only), f = 0 (OE, and WE),

VCC = 3.60V

17µA

ISB2 Automatic CE

Power-down

Current — CMOS

Inputs

CE > VCC – 0.2V,

VIN > VCC – 0.2V or VIN < 0.2V,

f = 0, VCC = 3.60V

17µA

Capacitance for all packages[7]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA= 25°C, f = 1 MHz,

VCC = VCC(typ.) 10 pF

COUT Output Capacitance 10 pF

Notes:

4. VIL(min.) = –2.0V for pulse durations less than 20 ns.

5. VIH(max) = VCC+0.75V for pulse durations less than 20 ns.

6. Full device AC operation assumes a 100 µs ramp time from 0 to VCC(min.) and 200 µs wait time after VCC stabilization.

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Thermal Resistance

Parameter Description Test Conditions BGA Unit

ΘJA Thermal Resistance

(Junction to Ambient) Still Air, soldered on a 3 x 4.5 inch, four-layer

printed circuit board 72 °C/W

ΘJC Thermal Resistance

(Junction to Case) 8.86 °C/W

AC Test Loads and Waveforms

Parameters 2.50V 3.0V Unit

R1 16667 1103 Ω

R2 15385 1554 Ω

RTH 8000 645 Ω

VTH 1.20 1.75 V

Data Retention Characteristics (Over the Operating Range)

Parameter Description Conditions Min. Typ.[3] Max. Unit

VDR VCC for Data Retention 1 V

ICCDR Data Retention Current VCC = 1V, CE > VCC − 0.2V,

VIN > VCC − 0.2V or VIN < 0.2V 0.8 3 µA

tCDR[7] Chip Deselect to Data Retention Time 0 ns

tR[8] Operation Recovery Time tRC ns

VCC

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10% 90%

10%

OUTPUT VTH

Equivalent to: THÉVENIN EQUIVALENT

ALL INPUT PULSES

RTH

Fall time: 1 V/ns

Rise Time: 1 V/ns

Data Retention Waveform

Notes:

7. Tested initially and after any design or process changes that may affect these parameters.

8. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) >100 µs.

1.5V

tCDR

VDR >1.5 V

DATA RETENTION MODE

VCC VCC (min.)

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Document #: 38-05577 Rev. *A Page 5 of 9

Switching Characteristics (Over the Operating Range)[9]

Parameter Description

45 ns

UnitMin. Max.

Read Cycle

tRC Read Cycle Time 45 ns

tAA Address to Data Valid 45 ns

tOHA Data Hold from Address Change 10 ns

tACE CE LOW to Data Valid 45 ns

tDOE OE LOW to Data Valid 22 ns

tLZOE OE LOW to Low Z[10] 5ns

tHZOE OE HIGH to High Z[10,11] 18 ns

tLZCE CE LOW to Low Z[10] 10 ns

tHZCE CE HIGH to High Z[10, 11] 18 ns

tPU CE LOW to Power-up 0 ns

tPD CE HIGH to Power-up 45 ns

Write Cycle[12]

tWC Write Cycle Time 45 ns

tSCE CE LOW to Write End 35 ns

tAW Address Set-up to Write End 35 ns

tHA Address Hold from Write End 0 ns

tSA Address Set-up to Write Start 0 ns

tPWE WE Pulse Width 35 ns

tSD Data Set-up to Write End 25 ns

tHD Data Hold from Write End 0 ns

tHZWE WE LOW to High Z[10, 11] 18 ns

tLZWE WE HIGH to Low Z[10] 10 ns

Switching Waveforms

Read Cycle No. 1 (Address Transition Controlled)[13, 14]

Notes:

9. Test Conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2,

input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.

10.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

11. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high-impedance state.

12.The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can

terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.

13.Device is continuously selected. OE, CE = VIL.

14.WE is HIGH for read cycle.

ADDRESS

DATA OUT PREVIOUS DATA VALID DATA VALID

tRC

tAA

tOHA

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MoBL®

Document #: 38-05577 Rev. *A Page 6 of 9

Read Cycle No. 2 (OE Controlled)[14, 15]

Write Cycle No. 1 (WE Controlled)[16, 18]

Notes:

15.Address valid prior to or coincident with CE transition LOW.

16.Data I/O is high impedance if OE = VIH.

17.During this period, the I/Os are in output state and input signals should not be applied.

18.If CE goes HIGH simultaneously with WE HIGH, the output remains in high-impedance state.

Switching Waveforms (continued)

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

DATA OUT HIGH IMPEDANCE IMPEDANCE

ICC

ISB

tHZOE

tHZCE

tPD

HIGH

VCC

SUPPLY

CURRENT

ADDRESS

tHD

tSD

tPWE

tSA

tHA

tAW

tWC

DATA I/O

ADDRESS

tHZOE

DATAIN VALID

NOTE17

tSCE

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Document #: 38-05577 Rev. *A Page 7 of 9

Write Cycle No. 2 (CE Controlled)[16, 18]

Write Cycle No. 3 (WE Controlled, OE LOW)[18]

Switching Waveforms (continued)

tWC

DATAIN VALID

tAW

tSA

tPWE

tHA

tHD

tSD

tSCE

ADDRESS

DATA I/O

ADDRESS

tHD

tSD

tLZWE

tSA

tHA

tAW

tWC

tHZWE

DATAIN VALID

NOTE 17

tPWE

tSCE

Truth Table

CE WE OE Inputs/Outputs Mode Power

H X X High Z Deselect/Power-down Standby (ISB)

L H L Data Out (I/O0–I/O7) Read Active (ICC)

L H H High Z Output Disabled Active (ICC)

L L X Data in (I/O0–I/O7) Write Active (ICC)

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Document #: 38-05577 Rev. *A Page 8 of 9

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company

names mentioned in this document may be the trademarks of their respective holders.

Ordering Information

Speed

(ns) Ordering Code Package

Diagram Package Type Operating

Range

45 CY62138EV30LL-45BVXI 51-85149 36-ball Very Fine Pitch BGA (6 mm × 8 mm × 1 mm) (Pb-free) Industrial

Package Diagrams

A1 CORNER

0.75

Ø0.30±0.05(36X)

Ø0.25MCAB

Ø0.05 M C

0.15(4X)

0.21±0.05

1.00 MAX

SEATING PLANE

0.55 MAX.

0.25 C

0.10 C

A1 CORNER

TOP VIEW BOTTOM VIEW

234

3.75

5.25

465231

6.00±0.10

8.00±0.10

6.00±0.10

1.875

2.625

0.26 MAX.

36-ball VFBGA (6 x 8 x 1 mm) (51-85149)

51-85149-*C

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Document #: 38-05577 Rev. *A Page 9 of 9

Document History Page

Document Title: CY62138EV30 2-Mbit (256K x 8) MoBL®Static RAM

Document Number: 38-05577

REV. ECN NO. Issue

Date Orig. of

Change Description of Change

** 237432 See ECN AJU New data sheet

*A 427817 See ECN NXR Removed 35 ns Speed Bin

Removed “L” version

Removed 32-pin TSOPII package from product Offering.

Changed ball C3 from DNU to NC.

Removed the redundant footnote on DNU.

Moved Product Portfolio from Page # 3 to Page #2.

Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from

1.5 mA to 2 mA at f = 1 MHz

Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax=1/tRC

ChangedISB1 andISB2 Typ.valuesfrom0.7µAto1µAandMax.valuesfrom

2.5 µA to 7 µA.

Changed VCC stabilization time in footnote #7 from 100 µs to 200 µs

Changed the AC test load capacitance from 50pF to 30pF on Page# 4

Changed VDR from 1.5V to 1V on Page# 4.

ChangedICCDR from 1µAto 3µAin theDataRetention Characteristicstable

on Page # 4.

Corected tRin Data Retention Characteristics from 100 µs to tRC ns

Changed tOHA,tLZCE,tLZWE from 6 ns to 10 ns

Changed tHZOE,tHZCE,tHZWE from 15 ns to 18 ns

Changed tLZOE from 3 ns to 5 ns

Changed tSCE and tAW from 40 ns to 35 ns

Changed tSD from 20 ns to 25 ns

Changed tPWE from 25 ns to 35 ns

Updated the Ordering Information table and replaced Package Name

column with Package Diagram.

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