Cypress CY62158EV30 User manual

8-Mbit (1024K x 8) Static RAM

CY62158EV30 MoBL®

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-05578 Rev. *D Revised April 19, 2007

Features

• Very high speed: 45 ns

— Wide voltage range: 2.20V–3.60V

• Pin compatible with CY62158DV30

• Ultra low standby power

— Typical standby current: 2 µA

— Maximum standby current: 8 µA

• Ultra low active power

— Typical active current: 1.8 mA @ f = 1 MHz

• Easy memory expansion with CE1, CE2, and OE features

• Automatic power down when deselected

• CMOS for optimum speed/power

• Offered in Pb-free 48-ball VFBGA, 44-pin TSOP II and

48-pin TSOP I packages[1]

Functional Description [2]

The CY62158EV30 is a high performance CMOS static RAM

organized as 1024K words by 8 bits. This device features

advanced circuit design to provide ultra low active current.

This is ideal for providing More Battery Life™ (MoBL®) in

portable applications such as cellular telephones. The device

also has an automatic power down feature that significantly

reduces power consumption. Placing the device into standby

mode reduces power consumption significantly when

deselected (CE1 HIGH or CE2LOW). The eight input and

output pins (IO0through IO7) are placed in a high impedance

state when the device is deselected (CE1 HIGH or CE2LOW),

the outputs are disabled (OE HIGH), or a write operation is in

progress (CE1 LOW and CE2HIGH and WE LOW).

To write to the device, take Chip Enables (CE1 LOW and CE2

HIGH) and Write Enable (WE) input LOW. Data on the eight

IO pins (IO0through IO7) is then written into the location

specified on the address pins (A0through A19).

To read from the device, take Chip Enables (CE1 LOW and

CE2HIGH) and OE LOW while forcing the WE HIGH. Under

these conditions, the contents of the memory location

specified by the address pins appear on the IO pins. See the

“Truth Table” on page 8 for a complete description of read and

write modes.

Logic Block Diagram

A0IO0

IO7

IO1

IO2

IO3

IO4

IO5

IO6

SENSE AMPS

POWER

DOWN

A13

A14

A15

A16

ROW DECODER

COLUMN DECODER

1024K x 8

ARRAY

DATA IN DRIVERS

A10

A11

A17

CE1

CE2

A12

A18

A19

Notes

1. For 48 pin TSOP I pin configuration and ordering information, please refer to CY62157EV30 Data sheet.

2. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.

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CY62158EV30 MoBL®

Document #: 38-05578 Rev. *D Page 2 of 11

Pin Configurations [3]

Product Portfolio

Product

VCC Range (V) Speed

(ns)

Power Dissipation

Operating ICC (mA)

Standby, ISB2 (µA)

f = 1 MHz f = fmax

Min Typ[4] Max Typ[4] Max Typ[4] Max Typ[4] Max

CY62158EV30LL 2.2 3.0 3.6 45 1.8 3 18 25 2 8

Top View

A11

A10

A3CE1

IO0

IO1

IO2

IO3

SS A7

CE2

A17

IO4

IO6

IO7

A15

A14

A13

A18 A19

A16 V

48-Ball VFBGA

14 31

VCC

A19

A18

A17

A16

VSS

CE1

IO 0

CE2

IO 1

VSS

IO 2

IO 3

VCC

IO 7

IO 6

IO 5

IO 4

A10

A11

A12

A13

A15 A14

Top View

44-Pin TSOPII

Notes

3. NC pins are not connected on the die.

4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA= 25°C.

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CY62158EV30 MoBL®

Document #: 38-05578 Rev. *D Page 3 of 11

Maximum Ratings

Exceeding the maximum ratings may impair the useful life of

the device. These user guidelines are not tested.

Storage Temperature ..................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage to Ground Potential –0.3V to VCC(max) + 0.3V

DC Voltage Applied to Outputs

in High-Z State[5, 6]......................... –0.3V to VCC(max) + 0.3V

DC Input Voltage[5, 6] ..................... –0.3V to VCC(max) + 0.3V

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage............................................ >2001V

(MIL-STD-883, Method 3015)

Latch up Current......................................................>200 mA

Operating Range

Product Range

Ambient

Temperature

(TA)

VCC[7]

CY62158EV30LL Industrial –40°C to +85°C 2.2V – 3.6V

Electrical Characteristics (Over the Operating Range)

Parameter Description Test Conditions 45 ns Unit

Min Typ[4] Max

VOH Output HIGH Voltage IOH = –0.1 mA 2.0 V

IOH = –1.0 mA, VCC >2.70V 2.4 V

VOL Output LOW Voltage IOL = 0.1 mA 0.4 V

IOL = 2.1 mA, VCC >2.70V 0.4 V

VIH Input HIGH Voltage VCC = 2.2V to 2.7V 1.8 VCC + 0.3V V

VCC = 2.7V to 3.6V 2.2 VCC + 0.3V V

VIIL Input LOW Voltage VCC = 2.2V to 2.7V –0.3 0.6 V

VCC = 2.7V to 3.6V –0.3 0.8 V

IIX Input Leakage Current GND < VI <VCC –1 +1 µA

IOZ Output Leakage Current GND < VO <VCC, Output Disabled –1 +1 µA

ICC VCC Operating Supply Current f = fmax = 1/tRC VCC = VCCmax

IOUT = 0 mA

CMOS levels

18 25 mA

f = 1 MHz 1.8 3 mA

ISB1 Automatic CE

Power down Current —

CMOS Inputs

CE1> VCC – 0.2V, CE2< 0.2V

VIN > VCC – 0.2V, VIN < 0.2V)

f = fmax (Address and Data Only),

f = 0 (OE and WE), VCC = 3.60V

28µA

ISB2[8] Automatic CE

Power down Current —

CMOS Inputs

CE1> VCC – 0.2V or CE2 <0.2V,

VIN > VCC – 0.2V or VIN < 0.2V,

f = 0, VCC = 3.60V

28µA

Capacitance[9]

Parameter Description Test Conditions Max Unit

CIN Input Capacitance TA= 25°C, f = 1 MHz,

VCC = VCC(typ)

10 pF

COUT Output Capacitance 10 pF

Notes

5. VIL(min) = –2.0V for pulse durations less than 20 ns.

6. VIH(max)= VCC + 0.75V for pulse duration less than 20 ns.

7. Full device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization.

8. Only chip enables (CE1and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.

9. Tested initially and after any design or process changes that may affect these parameters.

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CY62158EV30 MoBL®

Document #: 38-05578 Rev. *D Page 4 of 11

Thermal Resistance[9]

Parameter Description Test Conditions BGA TSOP II Unit

ΘJA Thermal Resistance

(Junction to Ambient)

Still Air, soldered on a 3 x 4.5 inch,

two-layer printed circuit board

72 76.88 °C/W

ΘJC Thermal Resistance

(Junction to Case)

8.86 13.52 °C/W

AC Test Loads and Waveforms

VCC

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10%

90%

10%

OUTPUT VTH

Equivalent to: THÉVENIN EQUIVALENT

ALL INPUT PULSES

RTH

Fall time: 1 V/ns

Rise Time: 1 V/ns

Parameters 2.5V 3.0V Unit

R1 16667 1103 Ω

R2 15385 1554 Ω

RTH 8000 645 Ω

VTH 1.20 1.75 V

Data Retention Characteristics (Over the Operating Range)

Parameter Description Conditions Min Typ[4] Max Unit

VDR VCC for Data Retention 1.5 V

ICCDR[8] Data Retention Current VCC = 1.5V, CE1> VCC − 0.2V

or CE2< 0.2V, VIN > VCC − 0.2V

or VIN < 0.2V

25µA

tCDR[9] Chip Deselect to Data

Retention Time

0ns

tR[10] Operation Recovery

Time

tRC ns

Data Retention Waveform

VCC, min

tCDR

VDR >1.5V

CE1

VCC

CE2

DATA RETENTION MODE

Note

10. Full Device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.

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Document #: 38-05578 Rev. *D Page 5 of 11

Switching Characteristics (Over the Operating Range) [11]

Parameter Description 45 ns Unit

Min Max

Read Cycle

tRC Read Cycle Time 45 ns

tAA Address to Data Valid 45 ns

tOHA Data Hold from Address Change 10 ns

tACE CE1 LOW and CE2 HIGH to Data Valid 45 ns

tDOE OE LOW to Data Valid 22 ns

tLZOE OE LOW to Low Z[12] 5ns

tHZOE OE HIGH to High Z[12, 13] 18 ns

tLZCE CE1 LOW and CE2 HIGH to Low Z[12] 10 ns

tHZCE CE1 HIGH or CE2 LOW to High Z[12, 13] 18 ns

tPU CE1 LOW and CE2 HIGH to Power Up 0 ns

tPD CE1 HIGH or CE2 LOW to Power Down 45 ns

Write Cycle[14]

tWC Write Cycle Time 45 ns

tSCE CE1 LOW and CE2 HIGH to Write End 35 ns

tAW Address Setup to Write End 35 ns

tHA Address Hold from Write End 0 ns

tSA Address Setup to Write Start 0 ns

tPWE WE Pulse Width 35 ns

tSD Data Setup to Write End 25 ns

tHD Data Hold from Write End 0 ns

tHZWE WE LOW to High Z[12, 13] 18 ns

tLZWE WE HIGH to Low Z[12] 10 ns

Notes

11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1V/ns), timing reference levels of VCC(typ)/2, input

pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in “AC Test Loads and Waveforms” on page 4.

12. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

13. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.

14. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these

signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.

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Document #: 38-05578 Rev. *D Page 6 of 11

Switching Waveforms

Read Cycle No. 1 (Address Transition Controlled)[15, 16]

Read Cycle No. 2 (OE Controlled)[16, 17]

ADDRESS

DATA OUT PREVIOUS DATA VALID DATA VALID

tRC

tAA

tOHA

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE

tHZOE

tHZCE

tPD

HIGH

ICC

ISB

IMPEDANCE

CE1

ADDRESS

CE2

DATA OUT

SUPPLY

CURRENT

VCC

Notes

15. Device is continuously selected. OE, CE1= VIL, CE2= VIH.

16. WE is HIGH for read cycle.

17. Address valid before or similar to CE1transition LOW and CE2transition HIGH.

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Document #: 38-05578 Rev. *D Page 7 of 11

Write Cycle No. 1 (WE Controlled)[14, 18, 19]

Write Cycle No. 2 (CE1 or CE2 Controlled)[14, 18, 19]

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tSCE

tWC

HZOE

VALID DATA

NOTE 20

CE1

ADDRESS

CE2

DATA IO

tWC

VALID DATA

tAW

tSA

tPWE

tHA

tHD

tSD

tSCE

CE1

ADDRESS

CE2

DATA IO

Notes

18. Data IO is high impedance if OE = VIH.

19. If CE1goes HIGH or CE2goes LOW simultaneously with WE HIGH, the output remains in high impedance state.

20. During this period, the IOs are in output state. Do not apply input signals.

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CY62158EV30 MoBL®

Document #: 38-05578 Rev. *D Page 8 of 11

Write Cycle No. 3 (WE Controlled, OE LOW)[19]

Truth Table

CE1CE2WE OE Inputs/Outputs Mode Power

H X X X High Z Deselect/Power Down Standby (ISB)

X L X X High Z Deselect/Power Down Standby (ISB)

L H H L Data Out Read Active (ICC)

L H H H High Z Output Disabled Active (ICC)

L H L X Data in Write Active (ICC)

Ordering Information

Speed

(ns) Ordering Code Package

Diagram Package Type Operating

Range

45 CY62158EV30LL-45BVXI 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free) Industrial

CY62158EV30LL-45ZSXI 51-85087 44-pin TSOP II (Pb-free)

Switching Waveforms (continued)

VALID DATA

tHD

tSD

tLZWE

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZWE

NOTE 20

CE1

ADDRESS

CE2

DATA IO

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Document #: 38-05578 Rev. *D Page 9 of 11

Package Diagrams

Figure 1. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150

A1 CORNER

0.75

Ø0.30±0.05(48X)

Ø0.25 M C A B

Ø0.05 M C

0.15(4X)

0.21±0.05

1.00 MAX

SEATING PLANE

0.55 MAX.

0.25 C

0.10 C

A1 CORNER

TOP VIEW BOTTOM VIEW

234

3.75

5.25

465231

6.00±0.10

8.00±0.10

6.00±0.10

1.875

2.625

0.26 MAX.

51-85150-*D

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Document #: 38-05578 Rev. *D Page 10 of 11

use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to

be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Figure 2. 44-Pin TSOP II, 51-85087

MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names

mentioned in this document are the trademarks of their respective holders.

Package Diagrams (continued)

51-85087-*A

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