Cypress Semiconductor MoBL CY62138F User manual

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 001-13194 Rev. *A Revised March 26, 2007

CY62138F MoBL®

2-Mbit (256K x 8) Static RAM

Features

• High speed: 45 ns

• Wide voltage range: 4.5 V – 5.5 V

• Pin compatible with CY62138V

• Ultra low standby power

— Typical standby current: 1µA

— Maximum standby current: 5 µA

• Ultra low active power

— Typical active current: 1.6 mA @ f = 1 MHz

• Easy memory expansion with CE1, CE2, and OE features

• Automatic power down when deselected

• CMOS for optimum speed and power

• Available in Pb-free 32-pin SOIC and 32-pin TSOP II

packages

Functional Description [1]

The CY62138F is a high performance CMOS static RAM

organized as 256K words by 8 bits. This device features

advanced circuit design to provide ultra low active current.

This is ideal for providing More Battery Life™ (MoBL®) in

portable applications such as cellular telephones. The device

also has an automatic power down feature that significantly

reduces power consumption when addresses are not toggling.

Placing the device into standby mode reduces power

consumption by more than 99% when deselected (CE1 HIGH

or CE2LOW).

To write to the device, take Chip Enable (CE1 LOW and CE2

HIGH) and Write Enable (WE) inputs LOW. Data on the eight

IO pins (IO0through IO7) is then written into the location

specified on the address pins (A0through A17).

To read from the device, take Chip Enable (CE1 LOW and CE2

HIGH) and output enable (OE) LOW while forcing Write

Enable (WE) HIGH. Under these conditions, the contents of

the memory location specified by the address pins appear on

the IO pins.

The eight input and output pins (IO0through IO7) are placed

in a high impedance state when the device is deselected (CE1

HIGH or CE2LOW), the outputs are disabled (OE HIGH), or

during a write operation (CE1 LOW and CE2HIGH and WE

LOW).

Logic Block Diagram

IO0

IO7

IO1

IO2

IO3

IO4

IO5

IO6

SENSE AMPS

POWER

DOWN

A13

A14

A15

A16

ROW DECODER

COLUMN DECODER

256K x 8

ARRAY

DATA IN DRIVERS

A10

A11

A17

CE1

CE2

A12

Note

1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.

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Document #: 001-13194 Rev. *A Page 2 of 10

CY62138F MoBL®

Pin Configuration [2]

Product Portfolio

Product VCC Range (V) Speed

(ns)

Power Dissipation

Operating ICC (mA) Standby ISB2 (µA)

f = 1MHz f = fmax

Min Typ [3] Max Typ [3] Max Typ [3] Max Typ [3] Max

CY62138FLL 4.5V 5.0V 5.5V 45 1.6 2.5 13 18 1 5

32-Pin SOIC/TSOP II Pinout

Top View

VSS

VCC

CE1

Notes

2. NC pins are not connected on the die.

3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA= 25°C.

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Document #: 001-13194 Rev. *A Page 3 of 10

CY62138F MoBL®

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Storage Temperature ................................ –65°C to + 150°C

Ambient Temperature with

Power Applied ........................................... –55°C to + 125°C

Supply Voltage to Ground

Potential ................................–0.5V to 6.0V (VCCmax + 0.5V)

DC Voltage Applied to Outputs

in High-Z state [4, 5] ................–0.5V to 6.0V (VCCmax + 0.5V)

DC Input Voltage [4, 5] ............ –0.5V to 6.0V (VCCmax + 0.5V)

Output Current into Outputs (LOW) ............................ 20 mA

Static Discharge Voltage ......................................... > 2001V

(MIL–STD–883, Method 3015)

Latch-up Current ................................................... > 200 mA

Operating Range

Device Range Ambient

Temperature VCC [6]

CY62138FLL Industrial –40°C to +85°C 4.5V to 5.5V

Electrical Characteristics (Over the Operating Range)

Parameter Description Test Conditions

45 ns

Unit

Min Typ [3] Max

VOH Output HIGH Voltage IOH = –1.0 mA 2.4 V

VOL Output LOW Voltage IOL = 2.1 mA 0.4 V

VIH Input HIGH Voltage VCC = 4.5V to 5.5V 2.2 VCC + 0.5 V

VIL Input LOW Voltage VCC = 4.5V to 5.5V –0.5 0.8 V

IIX Input Leakage Current GND < VI< VCC –1 +1 µA

IOZ Output Leakage Current GND < VO <VCC, Output Disabled –1 +1 µA

ICC VCC Operating Supply

Current

f = fmax = 1/tRC VCC = VCC(max)

IOUT = 0 mA

CMOS levels

13 18 mA

f = 1 MHz 1.6 2.5

ISB2 [7] Automatic CE Power Down

Current CMOS inputs

CE1> VCC – 0.2V or CE2 <0.2V

VIN > VCC – 0.2V or VIN < 0.2V,

f = 0, VCC = VCC(max)

15µA

Capacitance (For all packages) [8]

Parameter Description Test Conditions Max Unit

CIN Input capacitance TA= 25°C, f = 1 MHz,

VCC = VCC(typ)

10 pF

COUT Output capacitance 10 pF

Thermal Resistance [8]

Parameter Description Test Conditions SOIC TSOP II Unit

ΘJA Thermal Resistance

(Junction to Ambient)

Still air, soldered on a 3 × 4.5 inch

two-layer printed circuit board

44.53 44.16 °C/W

ΘJC Thermal Resistance

(Junction to Case)

24.05 11.97 °C/W

Notes

4. VIL(min) = –2.0V for pulse durations less than 20 ns.

5. VIH(max) = VCC+0.75V for pulse durations less than 20ns.

6. Full device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization.

7. Only chip enables (CE1and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.

8. Tested initially and after any design or process changes that may affect these parameters.

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Document #: 001-13194 Rev. *A Page 4 of 10

CY62138F MoBL®

AC Test Loads and Waveforms

Parameters 5.0V Unit

R1 1800 Ω

R2 990 Ω

RTH 639 Ω

VTH 1.77 V

Data Retention Characteristics (Over the Operating Range)

Parameter Description Conditions Min Typ [3] Max Unit

VDR VCC for Data Retention 2.0 V

ICCDR [7] Data Retention Current VCC= VDR, CE1> VCC − 0.2V or CE2< 0.2V,

VIN > VCC - 0.2V or VIN < 0.2V

15µA

tCDR [8] Chip Deselect to Data

Retention Time

0ns

tR [9] Operation Recovery Time tRC ns

Data Retention Waveform [10]

3.0V

VCC

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10%

90%

10%

Rise Time = 1 V/ns Fall Time = 1 V/ns

OUTPUT V

Equivalent to: THEVENIN EQUIVALENT

ALL INPUT PULSES

RTH

VCC(min)

tCDR

VDR >2.0V

DATA RETENTION MODE

VCC

Notes:

9. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.

10. CE is the logical combination of CE1and CE2. When CE1is LOW and CE2 is HIGH, CE is LOW; when CE1is HIGH or CE2is LOW, CE is HIGH.

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Document #: 001-13194 Rev. *A Page 5 of 10

CY62138F MoBL®

Switching Characteristics (Over the Operating Range) [11]

Parameter Description

45 ns

Unit

Min Max

Read Cycle

tRC Read Cycle Time 45 ns

tAA Address to Data Valid 45 ns

tOHA Data Hold from Address Change 10 ns

tACE CE1 LOW and CE2 HIGH to Data Valid 45 ns

tDOE OE LOW to Data Valid 22 ns

tLZOE OE LOW to Low-Z [12] 5ns

tHZOE OE HIGH to High-Z [12, 13] 18 ns

tLZCE CE1 LOW and CE2 HIGH to Low Z [12] 10 ns

tHZCE CE1 HIGH or CE2 LOW to High-Z [12, 13] 18 ns

tPU CE1 LOW and CE2 HIGH to power up 0 ns

tPD CE1 HIGH or CE2 LOW to power down 45 ns

Write Cycle [14]

tWC Write Cycle Time 45 ns

tSCE CE1 LOW and CE2 HIGH to Write End 35 ns

tAW Address Setup to Write End 35 ns

tHA Address Hold from Write End 0 ns

tSA Address Setup to Write Start 0 ns

tPWE WE Pulse Width 35 ns

tSD Data Setup to Write end 25 ns

tHD Data Hold from Write End 0 ns

tHZWE WE LOW to High-Z [12, 13] 18 ns

tLZWE WE HIGH to Low-Z [12] 10 ns

Notes

11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input

pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 4.

12. At any given temperature and voltage condition, tHZCE is less than tLZCE , tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

13. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.

14. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these

signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.

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Document #: 001-13194 Rev. *A Page 6 of 10

CY62138F MoBL®

Switching Waveforms

Read Cycle 1 (Address transition controlled) [15, 16]

Read Cycle No. 2 (OE controlled) [10, 16, 17]

Write Cycle No. 1 (WE controlled) [10, 14, 18, 19]

PREVIOUS DATA VALID DATA VALID

tAA

tOHA

tRC

ADDRESS

DATA OUT

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE

tHZOE

tHZCE

tPD

IMPEDANCE

ICC

ISB

HIGH

ADDRESS

DATA OUT

VCC

SUPPLY

CURRENT

DATA VALID

tHD

tSD

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZOE

ADDRESS

DATA IO

NOTE

Notes:

15. The device is continuously selected. OE, CE1= VIL, CE2= VIH.

16. WE is HIGH for read cycle.

17. Address valid before or similar to CE1transition LOW and CE2transition HIGH.

18. Data IO is high impedance if OE = VIH.

19. If CE1goes HIGH or CE2goes LOW simultaneously with WE HIGH, the output remains in high impedance state.

20. During this period, the IOs are in output state. Do not apply input signals.

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Document #: 001-13194 Rev. *A Page 7 of 10

CY62138F MoBL®

Write Cycle No. 2 (CE1 or CE2 controlled) [10, 14, 18, 19]

Write Cycle No. 3 (WE controlled, OE LOW) [10, 19]

Truth Table

CE WE OE Inputs/Outputs Mode Power

H X X High Z Deselect/Power Down Standby (ISB)

L H L Data Out Read Active (ICC)

L L X Data In Write Active (ICC)

L H H High Z Selected, Outputs Disabled Active (ICC)

Ordering Information

Speed

(ns) Ordering Code

Package

Diagram Package Type Operating

Range

45 CY62138FLL-45SXI 51-85081 32-pin Small Outline Integrated Circuit (Pb-free) Industrial

CY62138FLL-45ZSXI 51-85095 32-pin Thin Small Outline Package II (Pb-free)

Contact your local Cypress sales representative for availability of these parts.

Switching Waveforms (continued)

tWC

DATA VALID

tAW

tSA

tPWE

tHA

tHD

tSD

tSCE

ADDRESS

DATA IO

DATA VALID

tHD

tSD

tLZWE

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZWE

ADDRESS

DATA IO

NOTE

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Document #: 001-13194 Rev. *A Page 8 of 10

CY62138F MoBL®

Package Diagrams

Figure 1. 32-pin (450 Mil) Molded SOIC, 51-85081

0.546[13.868]

0.440[11.176]

0.101[2.565]

0.050[1.270]

0.014[0.355]

0.118[2.997]

0.004[0.102]

0.047[1.193]

0.006[0.152]

0.023[0.584]

0.793[20.142]

0.450[11.430]

0.566[14.376]

0.111[2.819]

0.817[20.751]

BSC.

0.020[0.508]

MIN.

MAX.

0.012[0.304]

0.039[0.990]

0.063[1.600]

SEATING PLANE

116

17 32

0.004[0.102]

51-85081-*B

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Document #: 001-13194 Rev. *A Page 9 of 10

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CY62138F MoBL®

Figure 2. 32-Pin TSOP II, 51-85095

MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names

mentioned in this document may be the trademarks of their respective holders.

Package Diagrams (continued)

51-85095-**

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Document #: 001-13194 Rev. *A Page 10 of 10

CY62138F MoBL®

Document History Page

Document Title: CY62138F MoBL®2-Mbit (256K x 8) Static RAM

Document Number: 001-13194

REV. ECN NO. Issue Date Orig. of

Change Description of Change

** 797956 See ECN VKN New Data Sheet

*A 940341 See ECN VKN Added footnote #7 related to ISB2 and ICCDR

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