Cypress Semiconductor CY7C1012DV33 User manual

Cypress Semiconductor Corporation • 198 Champion Court • San Jose

CA 95134-1709 • 408-943-2600

Document Number: 38-05610 Rev. *D Revised November 6, 2008

CY7C1012DV33

12-Mbit (512K X 24) Static RAM

Features

■

High speed

❐

= 10 ns

■

Low active power

❐

= 175 mA at 10 ns

■

Low CMOS standby power

❐

SB2

= 25 mA

■

Operating voltages of 3.3 ± 0.3V

■

2.0V data retention

■

Automatic power down when deselected

■

TTL compatible inputs and outputs

■

Available in Pb-free standard 119-ball PBGA

Functional Description

The CY7C1012DV33 is a high performance CMOS static RAM

organizedas512Kwordsby24bits.Eachdatabyteisseparately

controlled by the individual chip selects (CE

, CE

, and CE

controls the data on the I/O

– I/O

, while CE

controls the

data on I/O

– I/O

, and CE

controls the data on the data pins

I/O

– I/O

. This device has an automatic power down feature

that significantly reduces power consumption when deselected.

Writing the data bytes into the SRAM is accomplished when the

chipselectcontrollingthatbyteisLOWandthewrite enable input

(WE) input is LOW. Data on the respective input and output (I/O)

pins is then written into the location specified on the address pins

–A

). Asserting all of the chip selects LOW and write enable

LOW writesall 24 bitsofdataintotheSRAM.Output enable (OE)

is ignored while in WRITE mode.

Data bytes are also individually read from the device. Reading a

byte is accomplished when the chip select controlling that byte

is LOW and write enable (WE) HIGH, while output enable (OE)

remains LOW. Under these conditions, the contents of the

memory location specified on the address pins appear on the

specified data input and output (I/O) pins. Asserting all the chip

selects LOW reads all 24 bits of data from the SRAM.

The 24 I/O pins (I/O

– I/O

) are placed in a high impedance

state when all the chip selects are HIGH or when the output

enable (OE) is HIGH during a READ mode. For more infor-

mation, see the Truth Table on page 8.

Logic Block Diagram

COLUMN

DECODER

ROW DECODER

SENSE AMPS

INPUT BUFFER

512K x 24

ARRAY

I/O

– I/O

I/O

– I/O

, CE

I/O

– I/O

CONTROL LOGIC

(9:0)

(18:10)

[+] Feedback

CY7C1012DV33

Document Number: 38-05610 Rev. *D Page 2 of 11

Selection Guide

Description –10 Unit

Maximum Access Time 10 ns

Maximum Operating Current 175 mA

Maximum CMOS Standby Current 25 mA

Pin Configuration

Figure 1. 119-Ball PBGA (

Top View)

[1]

1234567

ANCAAAAANC

BNC A A CE

AANC

CI/O

NC CE

NC I/O

DI/O

I/O

EI/O

I/O

FI/O

I/O

GI/O

I/O

HI/O

I/O

JNC V

KI/O

I/O

LI/O

I/O

MI/O

I/O

NI/O

I/O

PI/O

I/O

RI/O

A NCNCNC AI/O

TNC A A WE AANC

UNC A A OE AANC

Note

1. NC pins are not connected on the die.

[+] Feedback

CY7C1012DV33

Document Number: 38-05610 Rev. *D Page 3 of 11

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with

Power Applied ............................................ –55°C to +125°C

Supply Voltage on V

Relative to GND

[2]

....–0.5V to +4.6V

DC Voltage Applied to Outputs

in High-Z State

[2]

..................................–0.5V to V

+ 0.5V

DC Input Voltage

[2]

...............................–0.5V to V

+ 0.5V

Current into Outputs (LOW) ........................................20 mA

Static Discharge Voltage............................................>2001V

(MIL-STD-883, Method 3015)

Latch Up Current.....................................................>200 mA

Operating Range

Range Ambient

Temperature V

Industrial –40°C to +85°C3.3V±0.3V

DC Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions

[3]

–10 Unit

Min Max

Output HIGH Voltage V

= Min, I

= –4.0 mA 2.4 V

Output LOW Voltage V

= Min, I

= 8.0 mA 0.4 V

Input HIGH Voltage 2.0 V

+ 0.3 V

IL[2]

Input LOW Voltage –0.3 0.8 V

Input Leakage Current GND < V

< V

–1 +1 μA

Output Leakage Current GND < V

OUT

, output disabled –1 +1 μA

Operating Supply

Current V

= Max, f = f

MAX

= 1/t

OUT

= 0 mA CMOS levels 175 mA

SB1

Automatic CE Power Down

Current —TTL Inputs Max V

, CE > V

> V

or V

< V

, f = f

MAX

30 mA

SB2

Automatic CE Power Down

Current —CMOS Inputs Max V

, CE > V

– 0.3V,

> V

– 0.3V, or V

< 0.3V, f = 0 25 mA

Notes

2. V

(min) = –2.0Vand V

(max) = V

+ 2V for pulse durations of less than 20 ns.

3. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE

or CE

2 ,

or CE

is LOW. When HIGH, CE indicates the CE

1 ,

2 ,

and

are HIGH.

[+] Feedback

CY7C1012DV33

Document Number: 38-05610 Rev. *D Page 4 of 11

Capacitance

Tested initially and after any design or process changes that may affect these parameters

Parameter Description Test Conditions Max Unit

Input Capacitance T

= 25°C, f = 1 MHz, V

= 3.3V 8 pF

OUT

I/O Capacitance 10 pF

Thermal Resistance

Tested initially and after any design or process changes that may affect these parameters.

Parameter Description Test Conditions 119-Ball

PBGA Unit

Thermal Resistance

(junction to ambient) Still air, soldered on a 3 × 4.5 inch,

four layer printed circuit board 20.31 °C/W

Thermal Resistance

(junction to case) 8.35 °C/W

Figure 2. AC Test Loads and Waveforms

[4]

90%

10%

3.0V

GND

90%

10%

All input pulses

3.3V

OUTPUT 5 pF*

(a) (b)

R1 317 Ω

351Ω

Fall Time:> 1V/ns

(c)

OUTPUT 50Ω

Z0= 50Ω

= 1.5V

30 pF*

Capacitive Load consists of all

components of the test environment

Rise Time > 1V/ns

*Including jig

and scope

Note

4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V

(3.0V). 100μs (t

power

) after reaching the minimum operating

, normal SRAM operation begins including reduction in V

to the data retention (V

CCDR

, 2.0V) voltage.

[+] Feedback

CY7C1012DV33

Document Number: 38-05610 Rev. *D Page 5 of 11

AC Switching Characteristics

Over the Operating Range

[5]

Parameter Description –10 Unit

Min Max

Read Cycle

power [6]

(Typical) to the First Access 100 μs

Read Cycle Time 10 ns

Address to Data Valid 10 ns

OHA

Data Hold from Address Change 3 ns

ACE

Active LOW to Data Valid

[3]

10 ns

DOE

OE LOW to Data Valid 5 ns

LZOE

OE LOW to Low Z

[7]

1ns

HZOE

OE HIGH to High Z

[7]

5ns

LZCE

Active LOW to Low Z

[3, 7]

3ns

HZCE

CE Deselect

HIGH to High Z

[3, 7]

5ns

Active LOW to Power Up

[3, 8]

0ns

CE Deselect

HIGH to Power Down

[3, 8]

10 ns

Write Cycle

[9, 10]

Write Cycle Time 10 ns

SCE

Active LOW to Write End

[3]

7ns

Address Setup to Write End 7 ns

Address Hold from Write End 0 ns

Address Setup to Write Start 0 ns

PWE

WE Pulse Width 7 ns

Data Setup to Write End 5.5 ns

Data Hold from Write End 0 ns

LZWE

WE HIGH to Low Z

[7]

3ns

HZWE

WE LOW to High Z

[7]

5ns

Notes

5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use

output loading as shown in part a) of Figure 2, unless specified otherwise.

6. t

POWER

gives the minimum amount of time that the power supply is at typical V

values until the first memory access is performed.

7. t

HZOE

, t

HZCE

, t

HZWE

, t

LZOE

, t

LZCE

, and t

LZWE

are specified with a load capacitance of 5 pF as in part (b) ofFigure 2. Transition is measured ±200 mV from steady state

voltage.

8. These parameters are guaranteed by design and are not tested.

9. The internal write time of the memory is defined by the overlap of CE

or CE

LOW and WE LOW. Chip enables must be active and WE must be LOW to initiate

a write. The transition of any of these signals terminate the write. The input data setup and hold timing are referenced to the leading edge of the signal that terminates

the write.

10.The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t

HZWE

and t

[+] Feedback

CY7C1012DV33

Document Number: 38-05610 Rev. *D Page 6 of 11

Data Retention Characteristics

Over the Operating Range

Parameter Description Conditions

[3]

Min Typ Max Unit

for Data Retention 2 V

CCDR

Data Retention Current V

= 2V, CE > V

– 0.2V,

> V

– 0.2V or V

< 0.2V 25 mA

CDR [11]

Chip Deselect to Data Retention

Time 0ns

R [12]

Operation Recovery Time t

Data Retention Waveform

Switching Waveforms

Figure 3. Read Cycle No. 1

[13, 14]

Figure 4. Read Cycle No. 2 (OE Controlled)

[3, 14, 15]

3.0V3.0V

CDR

DATA RETENTION MODE

PREVIOUS DATA VALID DATA VALID

OHA

ADDRESS

DATA OUT

50%

DATA VALID

ACE

DOE

LZOE

LZCE

HIGH IMPEDANCE

HZOE

HZCE

ADDRESS

DATA OUT

SUPPLY

CURRENT

HIGH

IMPEDANCE

Notes

11. Tested initially and after any design or process changes that may affect these parameters.

12.Full device operation requires linear V

ramp from V

to V

CC(min)

>50 μs or stable at V

CC(min)

>50 μs.

13.Device is continuously selected. OE, CE = V

14.WEis HIGH for read cycle.

15.Address valid before or similar to CEtransition LOW.

[+] Feedback

CY7C1012DV33

Document Number: 38-05610 Rev. *D Page 7 of 11

Figure 5. Write Cycle No. 1 (CE Controlled)

[3, 16, 17]

Figure 6. Write Cycle No. 2 (WE Controlled, OE HIGH During Write)

[3, 16, 17]

Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW)

[3, 17]

Switching Waveforms

(continued)

DATA VALID

PWE

SCE

DATA I/O

ADDRESS

PWE

SCE

HZOE

DATA

VALID

ADDRESS

DATA I/O

NOTE

DATA VALID

LZWE

PWE

SCE

HZWE

ADDRESS

DATA I/O NOTE

Notes

16.Data I/O is high impedance if OE= V

17.If CEgoes HIGH simultaneously with WE going HIGH, the output remains ina high impedance state.

18.During this period, the I/Os are in output state. Do not apply input signals.

[+] Feedback

CY7C1012DV33

Document Number: 38-05610 Rev. *D Page 8 of 11

Truth Table

OE WE I/O

– I/O

I/O

– I/O

I/O

– I/O

Mode Power

H H H X X High Z High Z High Z Power Down Standby (I

)

L H H L H Data Out High Z High Z Read Active (I

)

H L H L H High Z Data Out High Z Read Active (I

)

H H L L H High Z High Z Data Out Read Active (I

)

LLLLHFullDataOutFullDataOutFullDataOutRead Active(I

)

L H H X L Data In High Z High Z Write Active (I

)

H L H X L High Z Data In High Z Write Active (I

)

H H L X L High Z High Z Data In Write Active (I

)

L L L X L Full Data In Full Data In Full Data In Write Active (I

)

L L L H H High Z High Z High Z Selected,

Outputs Disabled Active (I

)

[+] Feedback

CY7C1012DV33

Document Number: 38-05610 Rev. *D Page 9 of 11

Ordering Information

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

10 CY7C1012DV33-10BGXI 51-85115 119-Ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-Free) Industrial

Package Diagram

Figure 8. 119-Ball PBGA (14 x 22 x 2.4 mm)

51-85115-*B

[+] Feedback

CY7C1012DV33

Document Number: 38-05610 Rev. *D Page 10 of 11

Document History Page

Document Title: CY7C1012DV33 12-Mbit (512K X 24) Static RAM

Document Number: 38-05610

Rev. ECN No. Orig. of

Change Submission

Date Description of Change

** 250650 SYT See ECN New data sheet

*A 469517 NXR See ECN Converted from Advance Information to Preliminary

Corrected typo in the Document Title

Removed –10 and –12 speed bins from product offering

Changed J7 Ball of BGA from DNU to NC

Removed Industrial Operating range from product offering

Included the Maximum ratings for Static Discharge Voltage and Latch Up Current

on page 3

Changed I

CC(Max)

from 220 mA to 150 mA

Changed I

SB1(Max)

from 70 mA to 30 mA

Changed I

SB2(Max)

from 40 mA to 25 mA

Specified the Overshoot specification in footnote 1

Updated the Truth Table

Updated the Ordering Information table

*B 499604 NXR See ECN Added note 1 for NC pins

Changed I

specification from 150 mA to 185 mA

Updated Test Condition for I

in DC Electrical Characteristics table

Added note for t

ACE

, t

LZCE

, t

HZCE

, t

, and t

SCE

in AC Switching Characteristics

Table on page 4

*C 1462585 VKN See ECN Converted from preliminary to final

Updated block diagram

Changed I

specification from 185 mA to 225 mA

Updated thermal specs

*D 2604677 VKN/PYRS 11/12/08 Removed Commercial operating range, Added Industrial operating range

Removed 8 ns speed bin, Added 10 ns speed bin,

Modified footnote# 3

[+] Feedback

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