Cypress Semiconductor CY7C1007B User manual
1M x 1 Static RAM
CY7C107B
CY7C1007B
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05030 Rev. ** Revised September 7, 2001
07B
Features
• High speed
—tAA = 12 ns
• CMOS for optimum speed/power
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
Functional Description
The CY7C107B and CY7C1007B are high-performance
CMOS static RAMs organized as 1,048,576 words by 1 bit.
Easy memory expansion is provided by an active LOW Chip
Enable (CE) and three-state drivers. These devices have an
automatic power-down feature that reduces power consump-
tion by more than 65% when deselected.
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the input pin
(DIN) is written into the memory location specified on the ad-
dress pins (A0through A19).
Reading from the devices is accomplished by taking Chip En-
able(CE)LOWwhileWriteEnable(WE)remainsHIGH.Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the data output (DOUT)
pin.
The output pin (DOUT) is placed in a high-impedance state
when the device is deselected (CE HIGH) or during a write
operation (CE and WE LOW).
The CY7C107B is available in a standard 400-mil-wide SOJ;
the CY7C1007B is available in a standard 300-mil-wide SOJ.
LogicBlock Diagram Pin Configuration
Top View
SOJ
512x2048
ARRA
Y
A5
A6
A7
COLUMN
DECODER
ROW DECODER
SENSE AMPS
POWER
DOWN
WE
CE
INPUT BUFFER
DOUT
DIN
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
14 15
16
20
19
18
17
21
24
23
22
12
13
25
28
27
26
GND
A11
A12
A13
A14
WE
VCC
A9
A10
CE
A0
DOUT DIN
A8
A7
A6
A2
A1
A4
NC
NC
A15
A16
A8
A12
A14
A16
A15
A10
A11
A13
A17
A18
A19
A17
A18
A19
A5
A3
A9
107B-1
107B-2
Selection Guide
7C107B-12
7C1007B-12 7C107B-15
7C1007B-15 7C107B-20
7C1007B-20 7C107B-25
7C1007B-25 7C107B-35
7C1007B-35
Maximum Access Time (ns) 12 15 20 25 35
Maximum Operating
Current (mA) 90 80 75 70 60
Maximum CMOS Standby
Current SB2 (mA) 2 2 2 2 2
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CY7C107B
CY7C1007B
Document #: 38-05030 Rev. ** Page 2 of 9
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .....................................−65°C to +150°C
Ambient Temperature with
Power Applied..................................................−55°C to +125°C
Supply Voltage on VCC Relative to GND[1] .....−0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1] .......................................−0.5V to VCC + 0.5V
DC Input Voltage[1].................................... −0.5V to VCC + 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TAis the “Instant On”case temperature.
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Operating Range
Range Ambient
Temperature[2] VCC
Commercial 0°C to +70°C 5V ±10%
Industrial −40°C to +85°C 5V ±10%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
7C107B-12
7C1007B-12 7C107B-15
7C1007B-15 7C107B-20
7C1007B-20
Min. Max. Min. Max. Min. Max. Unit
VOH Output HIGH
Voltage VCC =Min.,IOH =−4.0mA 2.4 2.4 2.4 V
VOL Output LOW
Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 0.4 V
VIH Input HIGH
Voltage 2.2 VCC+
0.3 2.2 VCC+
0.3 2.2 VCC+
0.3 V
VIL Input LOW
Voltage[1] −0.3 0.8 −0.3 0.8 −0.3 0.8 V
IIX Input Load Current GND <VI< VCC −1+1−1+1−1+1µA
IOZ Output Leakage
Current GND <VI <VCC,
Output Disabled –5+5–5+5–5+5µA
IOS Output Short
Circuit Current[3] VCC = Max., VOUT = GND −300 −300 −300 mA
ICC VCC Operating
Supply Current VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
90 80 75 mA
ISB1 Automatic CE
Power-Down
Current—TTL Inputs
Max. VCC, CE > VIH,
VIN >VIH or VIN < VIL,
f = f MAX
20 20 20 mA
ISB2 Automatic CE
Power-Down
Current—
CMOS Inputs
Max. VCC,
CE > VCC –0.3V,
VIN > VCC –0.3V or
VIN < 0.3V, f = 0
222mA
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CY7C107B
CY7C1007B
Document #: 38-05030 Rev. ** Page 3 of 9
Electrical Characteristics Over the Operating Range (continued)
Parameter Description Test Conditions
7C107B-25
7C1007B-25 7C107B-35
7C1007B-35
Min. Max. Min. Max. Unit
VOH Output HIGH
Voltage VCC = Min., IOH = −4.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.3 2.2 VCC + 0.3 V
VIL Input LOW Voltage[1] −0.3 0.8 −0.3 0.8 V
IIX Input Load Current GND <VI< VCC −1+1−1+1µA
IOZ Output Leakage
Current GND <VI <VCC,
Output Disabled −5+5−5+5µA
IOS Output Short
Circuit Current[3] VCC = Max., VOUT = GND −300 −300 mA
ICC VCC Operating
Supply Current VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
70 60 mA
ISB1 Automatic CE
Power-Down
Current—TTL Inputs
Max. VCC, CE > VIH,
VIN >VIH or VIN < VIL,
f = f MAX
20 20 mA
ISB2 Automatic CE
Power-Down
Current—CMOS Inputs
Max. VCC,
CE > VCC –0.3V,
VIN > VCC –0.3V or
VIN < 0.3V, f = 0
22mA
Capacitance[4]
Parameter Description Test Conditions Max. Unit
CIN:Addresses Input Capacitance TA= 25°C, f = 1 MHz,
VCC = 5.0V 7pF
CIN: Controls 10 pF
COUT Output Capacitance 10 pF
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
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CY7C107B
CY7C1007B
Document #: 38-05030 Rev. ** Page 4 of 9
AC Test Loads and Waveforms
3.0V
5V
OUTPUT
R1 480Ω
R2
255Ω
30 pF
INCLUDING
JIG AND
SCOPE
GND 90%
10% 90%
10%
≤ 3ns ≤ 3ns
5V
OUTPUT
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT 1.73V
Equivalentto: THÉVENIN EQUIVALENT
ALL INPUT PULSES
R2
255Ω
R1 480Ω
167Ω
107-3
107-4
Switching Characteristics[5]Over the Operating Range
7C107B-12
7C1007B-12 7C107B-15
7C1007B-15 7C107B-20
7C1007B-20 7C107B-25
7C1007B-25 7C107B-35
7C1007B-35
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 12 15 20 25 35 ns
tAA Address to Data Valid 12 15 20 25 35 ns
tOHA Data Hold from Address
Change 33333ns
tACE CE LOW to Data Valid 12 15 20 25 35 ns
tLZCE CE LOW to Low Z[6] 33333ns
tHZCE CE HIGH to High Z[6, 7] 6781010ns
tPU CE LOW to Power-Up 0 0 0 0 0 ns
tPD CE HIGH to Power-Down 12 15 20 25 35 ns
WRITE CYCLE[8]
tWC Write Cycle Time 12 15 20 25 35 ns
tSCE CE LOW to Write End 10 12 15 20 25 ns
tAW Address Set-Up to Write
End 10 12 15 20 25 ns
tHA Address Hold from Write
End 00000ns
tSA Address Set-Up to Write
Start 00000ns
tPWE WE Pulse Width 10 12 15 20 25 ns
tSD Data Set-Up to Write End 7 8 10 15 20 ns
tHD Data Hold from Write End 0 0 0 0 0 ns
tLZWE WE HIGH to Low Z[6] 33333ns
tHZWE WE LOW to High Z[6, 7] 6781010ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device.
7. tHZCE and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CELOW and WELOW. CE andWEmust be LOW to initiatea write, andthe transition of any ofthese
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
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CY7C1007B
Document #: 38-05030 Rev. ** Page 5 of 9
Switching Waveforms
Read Cycle No. 1[10, 11]
Read Cycle No. 2[11, 12]
Write Cycle No. 1 (CE Controlled)[13]
Notes:
9. No input may exceed VCC + 0.5V.
10. Device is continuously selected, CE= VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
107-6
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tLZCE
tPU
HIGH IMPEDANCE
tHZCE
tPD
HIGH
ICC
ISB
IMPEDANCE
ADDRESS
CE
DATA OUT
VCC
SUPPLY
CURRENT 107-7
DATA VALID
tSCE
tAW
tSA
tPWE
tHA
tHD
tSD
tWC
HIGH IMPEDANCE
ADDRESS
CE
WE
DATA OUT
DATA IN
107-8
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CY7C1007B
Document #: 38-05030 Rev. ** Page 6 of 9
Write Cycle No. 2 (WE Controlled)[13]
Note:
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains ina high-impedance state.
Switching Waveforms (continued)
tWC
DATA VALID
DATA UNDEFINED HIGH IMPEDANCE
tSCE
tAW
tSA tPWE tHA
tHD
tHZWE tLZWE
tSD
ADDRESS
CE
WE
DATA OUT
DATA IN
107-9
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CY7C1007B
Document #: 38-05030 Rev. ** Page 7 of 9
Package Diagrams
Truth Table
CE WE DOUT Mode Power
H X High Z Power-Down Standby (ISB)
L H Data Out Read Active (ICC)
L L High Z Write Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
12 CY7C107B-12VC V28 28-Lead (400-Mil) Molded SOJ Commercial
CY7C1007B-12VC V28 28-Lead (300-Mil) Molded SOJ Commercial
15 CY7C107B-15VC V28 28-Lead (400-Mil) Molded SOJ Commercial
CY7C1007B-15VC V28 28-Lead (300-Mil) Molded SOJ Commercial
15 CY7C107B-15VI V28 28-Lead (400-Mil) Molded SOJ Industrial
CY7C1007B-15VI V28 28-Lead (300-Mil) Molded SOJ Industrial
20 CY7C107B-20VC V28 28-Lead (400-Mil) Molded SOJ Commercial
CY7C1007B-20VC V28 28-Lead (300-Mil) Molded SOJ Commercial
25 CY7C107B-25VC V28 28-Lead (400-Mil) Molded SOJ Commercial
CY7C1007B-25VC V28 28-Lead (300-Mil) Molded SOJ Commercial
Contact factory for “L”version availability.
28-Lead (400-Mil) Molded SOJ V28
51-85032-A
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CY7C107B
CY7C1007B
Document #: 38-05030 Rev. ** Page 8 of 9
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitryembodiedin a CypressSemiconductorproduct.Nor does itconvey orimply any license underpatent or other rights.Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
28-Lead (300-Mil) Molded SOJ V21
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CY7C107B
CY7C1007B
Document #: 38-05030 Rev. ** Page 9 of 9
Document Title: CY7C107B/CY7C1007B 1M x 1 Static RAM
Document Number: 38-05030
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 109950 12/02/01 SZV Change from Spec number: 38-01116 to 38-05030
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