Cypress Semiconductor CY62148EV30 User manual
MoBL®CY62148EV30
4-Mbit (512K x 8) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05576 Rev. *G Revised August 4, 2008
Features
■Very high speed: 45 ns
❐Wide voltage range: 2.20V to 3.60V
■Temperature ranges
❐Industrial: –40°C to +85°C
❐Automotive-A: –40°C to +85°C
■Pin compatible with CY62148DV30
■Ultra low standby power
❐Typical standby current: 1 μA
❐Maximum standby current: 7 μA (Industrial)
■Ultra low active power
❐Typical active current: 2 mA at f = 1 MHz
■Easy memory expansion with CE, and OE features
■Automatic power down when deselected
■CMOS for optimum speed and power
■Available in Pb-free 36-ball VFBGA, 32-pin TSOP II and 32-pin
SOIC [1] packages
Functional Description
The CY62148EV30[2] is a high performance CMOS static RAM
organized as 512K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Placing the device into standby mode reduces
power consumption by more than 99 percent when deselected
(CE HIGH). The eight input and output pins (IO0through IO7) are
placed in a high impedance state when the device is deselected
(CE HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight IO pins (IO0through IO7) is
then written into the location specified on the address pins (A0
through A18).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the IO pins.
Notes
1. SOIC package is available only in 55 ns speed bin.
2. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
Logic Block Diagram
A0IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
A1
A2
A3
A4
A5
A6
A7
A8
A9
SENSE AMPS
POWER
DOWN
CE
WE
OE
A13
A14
A15
A16
A17
ROW DECODER
COLUMN DECODER
512K x 8
ARRAY
INPUT BUFFER
A10
A11
A12
A18
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MoBL®CY62148EV30
Document #: 38-05576 Rev. *G Page 2 of 12
Pin Configuration [1, 3]
Product Portfolio
Product Range VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC (mA) Standby ISB2
(µA)
f = 1 MHz f = fmax
Min Typ[4] Max Typ[4] Max Typ[4] Max Typ[4] Max
CY62148EV30LL VFBGA Ind’l 2.2 3.0 3.6 45 2 2.5 15 20 1 7
TSOP II Ind’l/Auto-A
SOIC Ind’l 2.2 3.0 3.6 55 2 2.5 15 20 1 7
A
15
V
CC
A
13
A12
A5
NC
WE A
7
IO4
IO5
A4
IO6
IO7
V
ss
A11
A10
A
1
V
SS
IO0
A
2
A
8
A6
A
3
A
0
V
cc
IO1
IO 2
IO 3
A17
A
18
A16
CE
OE
A
9
A
14
D
E
B
A
C
F
G
H
NC
36-Ball VFBGA Pinout
Top View
1
2
3
4
5
6
7
8
9
10
11
14
31
32
12
13
16
15
29
30
21
22
19
20
27
28
25
26
17
18
23
24
32-Pin SOIC/TSOP II Pinout
Top View
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
VSS
VCC
A
18
WE
OE
CE
Notes
3. NC pins are not connected on the die.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA= 25°C.
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MoBL®CY62148EV30
Document #: 38-05576 Rev. *G Page 3 of 12
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature .................................. –65°C to +150°C
Ambient Temperature with
Power Applied .............................................. 55°C to +125°C
Supply Voltage to Ground
Potential..........................................–0.3V to VCC(max) + 0.3V
DC Voltage Applied to Outputs
in High-Z State [5, 6] ........................–0.3V to VCC(max) + 0.3V
DC Input Voltage [5, 6] .....................–0.3V to VCC(max) + 0.3V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current.....................................................> 200 mA
Operating Range
Product Range Ambient
Temperature VCC [7]
CY62148EV30 Ind’l/Auto-A –40°C to +85°C 2.2V to 3.6V
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions - 45 (Ind’l/Auto-A) - 55 [1]
Unit
Min Typ[4] Max Min Typ[4] Max
VOH Output HIGH
Voltage
IOH = –0.1 mA 2.0 2.0 V
IOH = –1.0 mA, VCC >2.70V 2.4 2.4 V
VOL Output LOW
Voltage
IOL = 0.1 mA 0.4 0.2 V
IOL = 2.1 mA, VCC >2.70V 0.4 0.4 V
VIH Input HIGH
Voltage
VCC = 2.2V to 2.7V 1.8 VCC + 0.3V 1.8 VCC + 0.3V V
VCC= 2.7V to 3.6V 2.2 VCC + 0.3V 2.2 VCC + 0.3V V
VIL Input LOW
Voltage
VCC = 2.2V to 2.7V For VFBGA and
TSOP II package
–0.3 0.6 V
For SOIC package –0.3 0.4 [8] V
VCC = 2.7V to 3.6V For VFBGA and
TSOP II package
–0.3 0.8 V
For SOIC package –0.3 0.6 [8]
IIX Input Leakage
Current
GND < VI< VCC –1 +1 –1 +1 μA
IOZ Output Leakage
Current
GND < VO <VCC, Output Disabled –1 +1 –1 +1 μA
ICC VCC Operating
Supply Current
f = fmax = 1/tRC VCC = VCC(max),
IOUT = 0 mA,
CMOS levels
15 20 15 20 mA
f = 1 MHz 2 2.5 2 2.5
ISB1 Automatic CE
Power Down
Current — CMOS
Inputs
CE > VCC – 0.2V,
VIN >VCC – 0.2V, VIN < 0.2V
f = fmax (Address and Data Only),
f = 0 (OE and WE), VCC = 3.60V
17 17μA
ISB2 [9] Automatic CE
Power Down
Current — CMOS
Inputs
CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.60V
17 17μA
Notes
5. VIL(min) = –2.0V for pulse durations less than 20 ns.
6. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.
7. Full device AC operation assumes a minimum of 100 μs ramp time from 0 to VCC(min) and 200 μs wait time after VCC stabilization.
8. Under DC conditions the device meets a VIL of 0.8V (for VCC range of 2.7V to 3.6V) and 0.6V (for VCC range of 2.2V to 2.7V). However, in dynamic conditions
Input LOW voltage applied to the device must not be higher than 0.6V and 0.4V for the above ranges. This is applicable to SOIC package only. Please refer to
AN13470 for details.
9. Only chip enable (CE) must be HIGH at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
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MoBL®CY62148EV30
Document #: 38-05576 Rev. *G Page 4 of 12
Capacitance (For All packages) [10]
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz,
VCC = VCC(typ)
10 pF
COUT Output Capacitance 10 pF
Thermal Resistance [10]
Parameter Description Test Conditions VFBGA
Package
TSOP II
Package
SOIC
Package Unit
ΘJA Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 x 4.5 inch,
two-layer printed circuit board
72 75.13 55 °C/W
ΘJC Thermal Resistance
(Junction to Case)
8.86 8.95 22 °C/W
AC Test Loads and Waveforms
Parameters 2.50V 3.0V Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
RTH 8000 645 Ω
VTH 1.20 1.75 V
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Typ [4] Max Unit
VDR VCC for Data Retention 1.5 V
ICCDR [9] Data Retention Current VCC = 1.5V, CE > VCC – 0.2V,
VIN >VCC – 0.2V or VIN <
0.2V
Ind’l/Auto-A 0.8 7 μA
tCDR [10] Chip Deselect to Data Retention Time 0 ns
tR [11] Operation Recovery Time tRC ns
Data Retention Waveform
VCC
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THEVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
VCC(min)
VCC(min)
tCDR
VDR >1.5V
DATA RETENTION MODE
tR
VCC
CE
Notes
10. Tested initially and after any design or process changes that may affect these parameters.
11. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs.
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MoBL®CY62148EV30
Document #: 38-05576 Rev. *G Page 5 of 12
Switching Characteristics
(Over the Operating Range) [12]
Parameter Description - 45 (Ind’l/Auto-A) - 55 [1]
Unit
Min Max Min Max
Read Cycle
tRC Read Cycle Time 45 55 ns
tAA Address to Data Valid 45 55 ns
tOHA Data Hold from Address Change 10 10 ns
tACE CE LOW to Data Valid 45 55 ns
tDOE OE LOW to Data Valid 22 25 ns
tLZOE OE LOW to Low Z [13] 55ns
tHZOE OE HIGH to High Z [13, 14] 18 20 ns
tLZCE CE LOW to Low Z [13] 10 10 ns
tHZCE CE HIGH to High Z [13, 14] 18 20 ns
tPU CE LOW to Power Up 0 0 ns
tPD CE HIGH to Power Up 45 55 ns
Write Cycle [15]
tWC Write Cycle Time 45 55 ns
tSCE CE LOW to Write End 35 40 ns
tAW Address Setup to Write End 35 40 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Setup to Write Start 0 0 ns
tPWE WE Pulse Width 35 40 ns
tSD Data Setup to Write End 25 25 ns
tHD Data Hold from Write End 0 0 ns
tHZWE WE LOW to High Z [13, 14] 18 20 ns
tLZWE WE HIGH to Low Z [13] 10 10 ns
Notes
12. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4.
13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
14. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state.
15. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
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MoBL®CY62148EV30
Document #: 38-05576 Rev. *G Page 6 of 12
Switching Waveforms
Figure 1. Read Cycle No. 1 (Address Transition Controlled) [16, 17]
Figure 2. Read Cycle No. 2 (OE Controlled) [17, 18]
Figure 3. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [19, 20]
PREVIOUS DATA VALID DATA VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
IMPEDANCE
ICC
ISB
HIGH
ADDRESS
CE
DATA OUT
VCC
SUPPLY
CURRENT
OE
DATA VALID
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
ADDRESS
CE
WE
DATA IO
OE
NOTE
21
Notes
16. Device is continuously selected. OE, CE = VIL.
17. WE is HIGH for read cycles.
18. Address valid before or similar to CE transition LOW.
19. Data IO is high impedance if OE = VIH.
20. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
21. During this period, the IOs are in output state. Do not apply input signals.
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MoBL®CY62148EV30
Document #: 38-05576 Rev. *G Page 7 of 12
Figure 4. Write Cycle No. 2 (CE Controlled) [19, 20]
Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW) [20]
Truth Table
CE WE OE Inputs/Outputs Mode Power
H X X High Z Deselect/Power down Standby (ISB)
L H L Data Out Read Active (ICC)
L H H High Z Output Disabled Active (ICC)
L L X Data in Write Active (ICC)
Switching Waveforms (continued)
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
ADDRESS
CE
DATA IO
WE
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
ADDRESS
CE
WE
DATA IO
NOTE
21
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MoBL®CY62148EV30
Document #: 38-05576 Rev. *G Page 8 of 12
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
45 CY62148EV30LL-45BVXI 51-85149 36-ball Very Fine Pitch Ball Grid Array (Pb-free) Industrial
CY62148EV30LL-45ZSXI 51-85095 32-pin Thin Small Outline Package II (Pb-free)
CY62148EV30LL-45ZSXA 51-85095 32-pin Thin Small Outline Package II (Pb-free) Automotive-A
55 CY62148EV30LL-55SXI 51-85081 32-pin Small Outline Integrated Circuit (Pb-free) Industrial
Contact your local Cypress sales representative for availability of these parts.
Package Diagrams
Figure 6. 36-ball VFBGA (6 x 8 x 1 mm) (51-85149)
A
1
A1 CORNER
0.75
0.75
Ø0.30±0.05(36X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.21±0.05
1.00 MAX
C
SEATING PLANE
0.55 MAX.
0.25 C
0.10 C
A1 CORNER
TOP VIEW BOTTOM VIEW
234
3.75
5.25
B
C
D
E
F
G
H
65
465231
D
H
F
G
E
C
B
A
6.00±0.10
8.00±0.10
A
8.00±0.10
6.00±0.10
B
1.875
2.625
0.26 MAX.
51-85149-*C
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MoBL®CY62148EV30
Document #: 38-05576 Rev. *G Page 9 of 12
Figure 7. 32-pin TSOP II (51-85095)
Package Diagrams (continued)
51-85095-**
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MoBL®CY62148EV30
Document #: 38-05576 Rev. *G Page 10 of 12
Figure 8. 32-pin (450 MIL) Molded SOIC (51-85081)
Package Diagrams (continued)
0.546[13.868]
0.440[11.176]
0.101[2.565]
0.050[1.270]
0.014[0.355]
0.118[2.997]
0.004[0.102]
0.047[1.193]
0.006[0.152]
0.023[0.584]
0.793[20.142]
0.450[11.430]
0.566[14.376]
0.111[2.819]
0.817[20.751]
BSC.
0.020[0.508]
MIN.
MAX.
0.012[0.304]
0.039[0.990]
0.063[1.600]
SEATING PLANE
116
17 32
0.004[0.102]
51-85081-*B
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