KINTEX-7 FPGA Development Board AX7325B User Manual
is the voltage of each BANK of FPGA, including BANK0, BANK12~18,
BANK32~34. On the AX7325B development board, BANK12~13 is connected
to the FMC connector. The default voltage of VCCO is 2.5V, which enables IO to
support LVDS interface. BANK16~18, BANK33~35 need to connect DDR3
memory and DDR3 chip, BANK voltage is 1.5V, other BANK voltage is 3.3V.
VMGTAVCC is the supply voltage of the internal GTP transceiver of the FPGA,
connected to 1.0V, VMGTAVTT is the termination voltage of the GTP transceiver,
connected to 1.2V.
The KINTEX-7 FPGA system requires that the power-up sequence be
powered by VCCINT, then VCCBRAM, then VCCAUX and finally VCCO. If VCCINT and VCCBRAM
have the same voltage, they can be powered up at the same time. The order of
power outages is reversed. The power-up sequence of the GTP transceiver is
VCCINT, then VMGTAVCC, then VMGTAVTT. If VCCINT and VMGTAVCC have the same voltage,
they can be powered up at the same time. The power-off sequence is just the
opposite of the power-on sequence.
Part 3:DDR3 DRAM
TheAX7325B FPGA development board is equipped with four 512MB
DDR3 chips, model MT41K256M16HA-125 (Compatible with
MT41J256M16HA-125). Four DDR3 SDRAMs form a 64-bit bus width.
Because four DDR3 chips are connected to the HP port of the FPGA, the
DDR3 SDRAM can run at speeds up to 800MHz (data rate 1600Mbps), and
four DDR3 memory systems are directly connected to the BANK32, BANK33,
and BANK34 interfaces of the FPGA. The specific configuration of DDR3
SDRAM is shown in Table 3-1.
MT41K256M16HA-125
Or
MT41J256M16HA-125
