Xilinx Alveo U200 User manual
Revision History
The following table shows the revision history for this document.
Section Revision Summary
11/20/2019 Version 1.1.1
General updates. Editorial updates only. No technical content updates.
10/31/2019 Version 1.1
All sections. Updated to the Vitis™ unified software platform throughout.
02/15/2019 Version 1.0
Initial Xilinx release. N/A
Revision History
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Table of Contents
Revision History...............................................................................................................2
Chapter 1: Introduction.............................................................................................. 5
Block Diagram..............................................................................................................................7
Card Features...............................................................................................................................7
Card Specifications......................................................................................................................9
Design Flows................................................................................................................................ 9
Chapter 2: Card Installation and Configuration......................................... 14
Electrostatic Discharge Caution...............................................................................................14
Installing Alveo Data Center Accelerator Cards in Server Chassis......................................14
FPGA Configuration...................................................................................................................15
Chapter 3: Card Component Description........................................................ 16
UltraScale+ FPGA....................................................................................................................... 16
DDR4 DIMM Memory................................................................................................................16
Quad SPI Flash Memory........................................................................................................... 16
USB JTAG Interface.................................................................................................................... 17
FT4232HQ USB-UART Interface............................................................................................... 17
PCI Express Endpoint................................................................................................................17
QSFP28 Module Connectors.................................................................................................... 18
I2C Bus........................................................................................................................................18
Status LEDs.................................................................................................................................19
Card Power System................................................................................................................... 19
Appendix A: Xilinx Design Constraints (XDC) File...................................... 20
Appendix B: Regulatory and Compliance Information........................... 21
CE Directives.............................................................................................................................. 21
CE Standards..............................................................................................................................21
Compliance Markings............................................................................................................... 22
Appendix C: Additional Resources and Legal Notices............................. 23
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Xilinx Resources.........................................................................................................................23
Documentation Navigator and Design Hubs.........................................................................23
References..................................................................................................................................23
Please Read: Important Legal Notices................................................................................... 25
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Chapter 1
Introduction
IMPORTANT! Except where noted, this user guide applies to both the U200 and U250 cards.
The Xilinx® Alveo™ U200/U250 Data Center accelerator cards are peripheral component
interconnect express (PCIe®) Gen3 x16 compliant cards featuring the Xilinx Virtex® UltraScale+™
technology. These cards accelerate compute-intensive applicaons such as machine learning,
data analycs, video processing, and more. The Alveo U200/U250 Data Center accelerator cards
are available in passive and acve cooling conguraons. The following gure shows a passively
cooled Alveo U200 accelerator card.
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Figure 1: Alveo U200 Data Center Accelerator Card (Passive Cooling)
X23434-102419
CAUTION! The Alveo U200/U250 accelerator card with passive cooling is designed to be installed into a data
center server, where controlled air ow provides direct cooling. Due to the card enclosure, switches are not
accessible and LEDs are not visible (except for the triple-LED module DS3 that protrudes through the le front
end PCIe bracket). The card details in this user guide are provided to aid understanding of the card features. If
the cooling enclosure is removed from the card and the card is powered-up, external fan cooling airow MUST
be applied to prevent over-temperature shut-down and possible damage to the card electronics. Removing the
cooling enclosure voids the board warranty.
See Appendix C: Addional Resources and Legal Noces for references to documents, les, and
resources relevant to the Alveo U200/U250 accelerator cards.
Chapter 1: Introduction
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Block Diagram
The block diagram of the Alveo U200/U250 accelerator card is shown in the following gure.
Figure 2: Card Block Diagram
Clocks
U200: XCU200 D2104
U250: XCU250 D2104
PCIe GEN1/2/3 x 1/2/4/8/16
QSFP #2
XADC
LEDs
QSFP #1
QSPI
Power
288-pin DIMM interface
64-bit + ECC dual rank support
x4/x8 UDIMM support
PC4-2400 compatible
C0
288-pin DIMM interface
64-bit + ECC dual rank support
x4/x8 UDIMM support
PC4-2400 compatible
C2
288-pin DIMM interface
64-bit + ECC dual rank support
x4/x8 UDIMM support
PC4-2400 compatible
C3
288-pin DIMM interface
64-bit + ECC dual rank support
x4/x8 UDIMM support
PC4-2400 compatible
C1
X23433-102419
Card Features
The Alveo U200/U250 accelerator card features are listed in this secon. Detailed informaon
for each feature is provided in Chapter 3: Card Component Descripon.
• Alveo U200 accelerator card:
○Virtex UltraScale+ XCU200-2FSGD2104E FPGA
• Alveo U250 accelerator card:
○Virtex UltraScale+ XCU250-2LFIGD2104E FPGA
Chapter 1: Introduction
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• Memory (four independent dual-rank DDR4 interfaces)
○64 gigabyte (GB) DDR4 memory
○4x DDR4 16 GB, 2400 mega-transfers per second (MT/s), 64-bit with error correcng code
(ECC) DIMM
○x4/x8 unregistered dual inline memory module (UDIMM) support
•Conguraon opons
○1 gigabit (Gb) Quad Serial Peripheral Interface (SPI) ash memory
○Micro-AB universal serial bus (USB) JTAG conguraon port
• 16-lane PCI Express
• Two QSFP28 connectors 100G interfaces
• USB-to-UART FT4232HQ bridge with Micro-AB USB connector
• PCIe Integrated Endpoint block connecvity
○Gen1, 2, or 3 up to x16
• I2C bus
• Status LEDs
• Power management with system management bus (SMBus) voltage, current, and temperature
monitoring
• Dynamic power sourcing based on external power supplied
• 65W PCIe slot funconal with PCIe slot power only
• 150 W PCIe slot funconal with 110 A max VCCINT current PCIe slot power and 6-pin PCIe
AUX power cable connected
• 225 W PCIe slot funconal with 160 A max VCCINT current PCIe slot power and 8-pin PCIe
AUX power cable connected
• Onboard reprogrammable ash conguraon memory
• Front panel JTAG and universal asynchronous receiver-transmier (UART) access through the
USB port
• FPGA congurable over USB/JTAG and Quad SPI conguraon ash memory
Chapter 1: Introduction
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Card Specifications
Dimensions
Height: 4.376 inch (11.115 cm)
PCB thickness (±5%): 0.062 inch (0.157 cm)
Card length, passive heat sink: 9.2 inch (23.4 cm)
Card thickness with heat sink enclosure installed:
Passive: 1.44 inch (3.66 cm)
Note: A 3D model of this card is not available.
Environmental
Temperature
Operang: 0°C to +45°C
Storage: –25°C to +60°C
Humidity
10% to 90% non-condensing
Operating Voltage
PCIe® slot +12 VDC, +3.3 VDC, +3.3 VAUXDC, External +12 VDC
Design Flows
The preferred opmal design ow for targeng the Alveo Data Center accelerator card uses the
Vis™ unied soware plaorm. However, tradional design ows, such as RTL or HLx are also
supported using the Vivado® Design Suite tools. The following gure shows a summary of the
design ows.
Chapter 1: Introduction
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Figure 3: Alveo Data Center Accelerator Card Design Flows
High complexity
Slowest
High
Simplicity
Time to Market
Hardware Expertise Required
Complexity abstracted
Fastest
Low
RTL Flow HLx Flow (IP integrator)
Traditional Flows
Target Platform
Vitis
X22272-020419
Requirements for the dierent design ows are listed in the following table.
Table 1: Requirements to Get Started with Alveo Data Center Accelerator Card Design
Flows
RTL Flow HLx Flow Vitis
Flow documentation UG9491UG8952UG13013
Hardware documentation UG1289 UG1289 N/A
Vivado tools support Board support XDC Board support XDC N/A
Programming the FPGA Vivado Hardware Manager Vivado Hardware Manager
Notes:
1. UltraFast Design Methodology Guide for the Vivado Design Suite (UG949).
2. Vivado Design Suite User Guide: System-Level Design Entry (UG895). See “Using the Vivado Design Suite Platform Board
Flow” in Chapter 2 and Appendix A.
3. Getting Started with Alveo Data Center Accelerator Cards (UG1301).
For either the RTL or HLx ow, designers can start by targeng the Alveo Data Center
accelerator card in the Vivado® tools. In the Vivado Design Suite, select Create New Project →
RTL Project, and then select the Alveo Data Center accelerator U200 card as shown in the
following gure.
Chapter 1: Introduction
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