Xilinx ML605 Operation instructions

AXI Interface Based

ML605/SP605 MicroBlaze

Processor Subsystem

Hardware Tutorial

UG669 (v3.0) March 15, 2011

ML605/SP605 Hardware Tutorial www.xilinx.com UG669 (v3.0) March 15, 2011

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Revision History

The following table shows the revision history for this document.

Date Version Revision

10/05/10 1.0 Initial Xilinx release.

12/21/10 2.0 Tutorial procedures have been updated in accordance with ISE® Design Suite:

Embedded Edition, version 12.4.

03/15/11 3.0 Tutorial procedures have been updated in accordance with ISE Design Suite: Embedded

Edition, version 13.1.

ML605/SP605 Hardware Tutorial www.xilinx.com 3

UG669 (v3.0) March 15, 2011

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Hardware and Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Included Files and Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Executing the System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

System Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Hardware Platform Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Opening the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Examining the System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Generating the Hardware Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Exporting the Base Hardware Platform to SDK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Downloading and Verifying the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Customizing the Embedded Hardware Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Adding IP from the Xilinx IP Catalog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Adding the Perf_AXI core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Connecting the Bus Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Connecting Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Implementing and Downloading the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Testing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Next Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table of Contents

4www.xilinx.com ML605/SP605 Hardware Tutorial

UG669 (v3.0) March 15, 2011

ML605/SP605 Hardware Tutorial www.xilinx.com 5

UG669 (v3.0) March 15, 2011

AXI Interface Based ML605/SP605

MicroBlaze Processor Subsystem

Hardware Tutorial

Introduction

This tutorial provides the steps required to build and modify the Xilinx® ML605

MicroBlaze™ Processor Subsystem or the Xilinx SP605 MicroBlaze Processor Subsystem.

The tutorial starts with steps in building the basic subsystem. The basic subsystem is then

modified by adding the cores necessary to measure throughput on AXI Central DMA

(AXI_CDMA).

Additional information can be found in UG683, EDK Concepts, Tools, and Techniques.

Readers are encouraged to refer to UG683 during the execution of this tutorial. [Ref 1]

Users should allow approximately three hours to complete this entire tutorial.

Hardware and Software Requirements

The hardware and software requirements to run the basic tutorial are:

• Xilinx ML605 evaluation board or Xilinx SP605 evaluation board

• Two USB Type-A to Mini-B 5-pin cables

• Ethernet cable (straight-through)

• Serial communications utility program (e.g., Windows HyperTerminal or Tera Term)

• ISE® Design Suite: Embedded Edition 13.1 which includes:

• Integrated Software Environment (ISE)

• Embedded Development Kit (EDK

• Software Development Kit (SDK)

6www.xilinx.com ML605/SP605 Hardware Tutorial

UG669 (v3.0) March 15, 2011

Prerequisites

Prerequisites required to run the basic tutorial are:

• ML605 MicroBlaze Processor Subsystem:

• Proper hardware setup and software installation, as described in UG668, Getting

Started with the Virtex-6 FPGA ML605 Embedded Kit [Ref 2]

• Familiarity with the ML605 MicroBlaze Processor Subsystem, documented in

DS668, AXI Interface Based ML605 Embedded Kit MicroBlaze Processor Subsystem

Data Sheet [Ref 3]

• SP605 MicroBlaze Processor Subsystem:

• Proper hardware setup and software installation, as described in UG667, Getting

Started with the Spartan-6 FPGA SP605 Embedded Kit [Ref 4]

• Familiarity with the SP605 MicroBlaze Processor Subsystem, documented in

DS667, AXI Interface Based SP605 Embedded Kit MicroBlaze Processor Subsystem Data

Sheet [Ref 5]

• Familiarity with UG683, EDK Concepts, Tools, and Techniques, Chapter 1 (Introduction),

Chapter 3 (Using Xilinx Platform Studio), and Chapter 4 (Working with the Embedded

Platform) [Ref 1]

• General knowledge of FPGAs, digital design concepts, and microprocessors

• Basic familiarity with the ISE Design Suite

• Basic VHDL/Verilog knowledge

System Overview

This tutorial is based on the ML605/SP605 Embedded Kit MicroBlaze Processor

Subsystem. Readers are encouraged to refer to DS668, AXI Interface Based ML605 Embedded

Kit MicroBlaze Processor Subsystem Data Sheet [Ref 3] or DS667, AXI Interface Based SP605

Embedded Kit MicroBlaze Processor Subsystem Data Sheet [Ref 5] during the execution of this

tutorial.

ML605/SP605 Hardware Tutorial www.xilinx.com 7

UG669 (v3.0) March 15, 2011

Included Files and Systems

The Tutorial_Sandbox directory is a working area for this tutorial. It is provided as part

of the ML605 or SP605 Embedded Kit and contains the benchmarking IP cores that are

added to the base MicroBlaze Processor Subsystem to create the benchmarking system.

Figure 1 shows the directory structure for the Tutorial_Sandbox working area.

Note: Although this tutorial starts from the base ML605_System, or base SP605_System as

shown in Figure 1, the Tutorial_Sandbox directory contains the additional files necessary to build

the benchmarking system. To generate a new tutorial sandbox, copy the Tutorial_Sandbox

directory into the working area on the user’s computer.

X-Ref Target - Figure 1

Figure 1: Tutorial Sandbox Directory Structure

ML605_Embedded_Kit/

SP605_Embedded_Kit

Documentation

edkBmmFile_bd.bmm

system.xml

ise_top.bit (containsno bootloop)

system.ucf

SWHW

hw_platform

data

perf_axi_v1_00_a

pcores

BenchmarkDemo.elf

BenchmarkDemo

SDK_Export

Tutorial_Completed ML605_System/

SP605_System

MicroBlaze_ProcessorSubSystem

(XPSProject)

Tutorial_SandBox Benchmark_Demo

UG669_01_021711

board_test_platform SDK_Workspace

board_test_app

benchmark_demo

standalone

ise_top.ucf

ise_proj.xise

ise_proj.gise

ise_top.vhd

8www.xilinx.com ML605/SP605 Hardware Tutorial

UG669 (v3.0) March 15, 2011

Included Files and Systems

The directory structure of the completed tutorial (Tutorial_Completed) is shown in

Figure 2.

X-Ref Target - Figure 2

Figure 2: Completed Tutorial Directory Structure

ML605_Embedded_Kit/

SP605_Embedded_Kit

Documentation

edkBmmFile_bd.bmm

system.xml

ise_top.bit (containsno bootloop)

system.ucf

SWHW

hw_platform

data

BenchmarkDemo.elf

BenchmarkDemo

SDK_Export

Tutorial_Completed ML605_System/

SP605_System

MicroBlaze_ProcessorSubSystem

(XPSProject)

Tutorial_SandBox Benchmark_Demo

UG669_02_021711

board_test_platform SDK_Workspace

board_test_app

hello_world_0

board_test_platform

hello_world_bsp_0

hw_platform

board_test_app

benchmark_demo

standalone

perf_axi_v1_00_a

pcores

ise_top.ucf

ise_proj.xise

ise_proj.gise

ise_top.vhd

ML605/SP605 Hardware Tutorial www.xilinx.com 9

UG669 (v3.0) March 15, 2011

Executing the System

The ready_for_download directory contains the pre-built bitstream and ELF files for

the ML605 or SP605 MicroBlaze Processor Subsystem. The directory structure of the

ML605_System is shown in DS668, AXI Interface Based ML605 Embedded Kit MicroBlaze

Processor Subsystem Data Sheet [Ref 3]. The directory structure of the SP605_System is

shown in DS667, AXI Interface Based SP605 Embedded Kit MicroBlaze Processor Subsystem

Data Sheet [Ref 5].

The pre-built bitstream and ELF files file are used to verify that the software is properly

installed and that the board is set up correctly. To execute the system using these files,

follow these steps:

1. Connect a USB Type-A to Mini-B 5-pin cable between the ML605 or SP605 USB JTAG

connector and the host computer.

2. Verify that the USB cable is properly connected to the USB UART connection and the

host computer, as described in UG668, Getting Started with the Virtex-6 FPGA ML605

Embedded Development Kit [Ref 2], or UG667, Getting Started with the Spartan-6 FPGA

ML605 Embedded Development Kit [Ref 4].

3. If the board is not already powered on, power on the ML605 board.

4. Open and configure a serial communications terminal utility program with these

settings:

• Baud Rate: 9600

•Data:8 bit

•Parity:None

•Stop:1 bit

• Flow Control: None

Figure 3 shows the serial port setup window.

Note: The Port setting (COM1, COM2, COM3, COM4) can vary based on the system setup

and might be set up differently than shown in Figure 3. It should be set appropriately for the

user’s system.

X-Ref Target - Figure 3

Figure 3: Serial Communications Utility Configuration

UG669_03_092110

10 www.xilinx.com ML605/SP605 Hardware Tutorial

UG669 (v3.0) March 15, 2011

Executing the System

5. Configure and exercise the MicroBlaze Processor Subsystem by launching the Xilinx

Microprocessor Debugger (XMD). Open a command shell with the proper ISE Design

tool and EDK environment settings.

Note: To set environment variables, run the settings32.bat file located in the Xilinx

installation area. At the command prompt, type C:\Xilinx\13.1\ISE_DS\settings32.bat and

press Enter.

6. Execute these commands to download the design and connect to the MicroBlaze

processor:

For ML605:

$ cd ML605_Embedded_Kit/ML605_System/ready_for_download

$ xmd

XMD% fpga -f ise_top_download.bit

Note: This command downloads the hardware bitstream into the FPGA but does not

download the software application.

XMD% connect mb mdm

Note: This command connects to the MicroBlaze debug module.

For SP605:

$ cd SP605_Embedded_Kit/SP605_System/ready_for_download

$ xmd

XMD% fpga -f ise_top_download.bit

Note: This command downloads the hardware bitstream into the FPGA but does not

download the software application.

XMD% connect mb mdm

Note: This command connects to the MicroBlaze debug module.

7. XMD allows low-level visibility into the design. There are several useful XMD

commands to allow for the peeking and poking of registers and memory locations

within the system. For example, writes to and reads from the internal block RAM are

done as follows:

• For ML605:

XMD% mwr 0x62000000 0xDEADBEEF

XMD% mrd 0x62000000

The value 0xDEADBEEF should be returned:

62000000: DEADBEEF

As an example of register access, write to the GPIO register which outputs data to

the 8-bit GPIO LEDs on the ML605 board:

XMD% mwr 0x81420000 0xAA

The value written to this register is now reflected in the GPIO LEDs. The next write

changes the LED display:

XMD% mwr 0x81420000 0x55

Note: A read from this register always returns 0x00000000, as this is an output-only

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