Texas Instruments TMS320DM357 User manual

TMS320DM357 DMSoC Enhanced DirectMemory Access (EDMA3) Controller

User's Guide

Literature Number: SPRUG34November 2008

2 SPRUG34 – November 2008Submit Documentation Feedback

Contents
Preface .............................................................................................................................. 13
1 Introduction ............................................................................................................. 171.1 Overview..................................................................................................................... 181.2 Features ..................................................................................................................... 181.3 Terminology Used in This Document .................................................................................... 19
2 EDMA3 Architecture ................................................................................................. 212.1 Functional Overview ....................................................................................................... 222.1.1 EDMA3 Controller Block Diagram ............................................................................... 222.1.2 EDMA3 Channel Controller (EDMA3CC) ...................................................................... 222.1.3 EDMA3 Transfer Controller (EDMA3TC) ....................................................................... 242.2 Types of EDMA3 Transfers ............................................................................................... 252.2.1 A-Synchronized Transfers........................................................................................ 262.2.2 AB-Synchronized Transfers ...................................................................................... 272.3 Parameter RAM (PaRAM) ................................................................................................ 282.3.1 PaRAM Set ......................................................................................................... 292.3.2 EDMA3 Channel Parameter Set Fields ........................................................................ 312.3.3 Null PaRAM Set ................................................................................................... 332.3.4 Dummy PaRAM Set............................................................................................... 332.3.5 Dummy Versus Null Transfer Comparison ..................................................................... 332.3.6 Parameter Set Updates .......................................................................................... 332.3.7 Linking Transfers .................................................................................................. 352.4 Initiating a DMA Transfer .................................................................................................. 382.4.1 DMA Channel ...................................................................................................... 382.4.2 QDMA Channels .................................................................................................. 412.4.3 Comparison Between DMA and QDMA Channels ............................................................ 412.5 Completion of a DMA Transfer ........................................................................................... 422.5.1 Normal Completion ................................................................................................ 432.5.2 Early Completion .................................................................................................. 432.5.3 Dummy or Null Completion ...................................................................................... 432.6 Event, Channel, and PaRAM Mapping .................................................................................. 432.6.1 DMA Channel to PaRAM Mapping .............................................................................. 442.6.2 QDMA Channel to PaRAM Mapping............................................................................ 442.7 EDMA3 Channel Controller Regions .................................................................................... 452.7.1 Region Overview .................................................................................................. 452.7.2 Channel Controller Regions...................................................................................... 472.8 Chaining EDMA3 Channels ............................................................................................... 472.9 EDMA3 Interrupts .......................................................................................................... 492.9.1 Transfer Completion Interrupts .................................................................................. 492.9.2 EDMA3 Interrupt Servicing ....................................................................................... 512.9.3 Interrupt Evaluation Operations ................................................................................. 542.9.4 Error Interrupts ..................................................................................................... 54
SPRUG34 – November 2008 Contents 3Submit Documentation Feedback

www.ti.com
2.10 Event Queue(s) ............................................................................................................. 552.10.1 DMA/QDMA Channel to Event Queue Mapping ............................................................. 562.10.2 Queue RAM Debug Visibility ................................................................................... 562.10.3 Queue Resource Tracking ...................................................................................... 562.10.4 Performance Considerations ................................................................................... 562.11 EDMA3 Transfer Controller (EDMA3TC) ................................................................................ 572.11.1 Architecture Details .............................................................................................. 572.11.2 Error Generation .................................................................................................. 582.11.3 Debug Features .................................................................................................. 592.11.4 EDMA3TC Configuration ........................................................................................ 592.12 Event Dataflow .............................................................................................................. 602.13 EDMA3 Prioritization ....................................................................................................... 612.13.1 Channel Priority .................................................................................................. 612.13.2 Trigger Source Priority ........................................................................................... 622.13.3 Dequeue Priority .................................................................................................. 622.13.4 System (Transfer Controller) Priority .......................................................................... 622.14 EDMA3 Operating Frequency (Clock Control) ......................................................................... 622.15 Reset Considerations ...................................................................................................... 622.16 Power Management ........................................................................................................ 632.17 Emulation Considerations ................................................................................................. 63
3 EDMA3 Transfer Examples ........................................................................................ 653.1 Block Move Example ...................................................................................................... 663.2 Subframe Extraction Example ............................................................................................ 683.3 Data Sorting Example ..................................................................................................... 703.4 Peripheral Servicing Example ............................................................................................ 723.4.1 Nonbursting Peripherals .......................................................................................... 723.4.2 Bursting Peripherals .............................................................................................. 743.4.3 Continuous Operation ............................................................................................ 763.4.4 Ping-Pong Buffering ............................................................................................... 793.4.5 Transfer Chaining Examples ..................................................................................... 82
4 Registers ................................................................................................................. 854.1 Register Memory Maps .................................................................................................... 864.2 Parameter RAM (PaRAM) Entries ....................................................................................... 864.2.1 Channel Options Parameter (OPT) ............................................................................. 874.2.2 Channel Source Address Parameter (SRC) ................................................................... 894.2.3 A Count/B Count Parameter (A_B_CNT) ...................................................................... 894.2.4 Channel Destination Address Parameter (DST) .............................................................. 904.2.5 Source B Index/Destination B Index Parameter (SRC_DST_BIDX) ........................................ 904.2.6 Link Address/B Count Reload Parameter (LINK_BCNTRLD) ............................................... 914.2.7 Source C Index/Destination C Index Parameter (SRC_DST_CIDX) ....................................... 924.2.8 C Count Parameter (CCNT) ..................................................................................... 924.3 EDMA3 Channel Controller Control Registers ......................................................................... 934.3.1 Global Registers ................................................................................................... 974.3.2 Error Registers ................................................................................................... 1024.3.3 Region Access Enable Registers .............................................................................. 1104.3.4 Status/Debug Visibility Registers .............................................................................. 1124.3.5 DMA Channel Registers ........................................................................................ 1164.3.6 Interrupt Registers ............................................................................................... 128
4Contents SPRUG34 – November 2008Submit Documentation Feedback

www.ti.com

4.3.7 QDMA Registers ................................................................................................. 1344.4 EDMA3 Transfer Controller Control Registers ........................................................................ 1404.4.1 Peripheral Identification Register (PID) ....................................................................... 1414.4.2 EDMA3TC Configuration Register (TCCFG) ................................................................. 1424.4.3 EDMA3TC Channel Status Register (TCSTAT) ............................................................. 1434.4.4 Error Registers ................................................................................................... 1444.4.5 Read Rate Register (RDRATE) ................................................................................ 1494.4.6 EDMA3TC Channel Registers ................................................................................. 149

A Tips ....................................................................................................................... 163A.1 Debug Checklist ........................................................................................................... 163A.2 Miscellaneous Programming/Debug Tips .............................................................................. 164

B Setting Up a Transfer .............................................................................................. 165

SPRUG34 – November 2008 Contents 5Submit Documentation Feedback

www.ti.com
List of Figures
2-1 EDMA3 Controller Block Diagram ........................................................................................ 222-2 EDMA3 Channel Controller (EDMA3CC) Block Diagram ............................................................. 232-3 EDMA3 Transfer Controller (EDMA3TC) Block Diagram ............................................................. 242-4 Definition of ACNT, BCNT, and CCNT ................................................................................. 252-5 A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) ....................................................... 262-6 AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) ..................................................... 272-7 PaRAM Set .................................................................................................................. 292-8 Linked Transfer ............................................................................................................. 362-9 Link-to-Self Transfer ....................................................................................................... 372-10 QDMA Channel to PaRAM Mapping .................................................................................... 452-11 Shadow Region Registers ................................................................................................ 462-12 Interrupt Diagram ........................................................................................................... 512-13 Error Interrupt Operation .................................................................................................. 552-14 EDMA3 Prioritization ....................................................................................................... 613-1 Block Move Example ...................................................................................................... 663-2 Block Move Example PaRAM Configuration............................................................................ 673-3 Subframe Extraction Example ............................................................................................ 683-4 Subframe Extraction Example PaRAM Configuration ................................................................. 693-5 Data Sorting Example ..................................................................................................... 703-6 Data Sorting Example PaRAM Configuration .......................................................................... 713-7 Servicing Incoming ASP Data Example ................................................................................. 723-8 Servicing Incoming ASP Data Example PaRAM ....................................................................... 733-9 Servicing Peripheral Burst Example ..................................................................................... 743-10 Servicing Peripheral Burst Example PaRAM ........................................................................... 753-11 Servicing Continuous ASP Data Example .............................................................................. 763-12 Servicing Continuous ASP Data Example PaRAM .................................................................... 773-13 Servicing Continuous ASP Data Example Reload PaRAM ........................................................... 783-14 Ping-Pong Buffering for ASP Data Example ........................................................................... 803-15 Ping-Pong Buffering for ASP Example PaRAM ........................................................................ 803-16 Ping-Pong Buffering for ASP Example Pong PaRAM ................................................................. 813-17 Ping-Pong Buffering for ASP Example Ping PaRAM .................................................................. 823-18 Intermediate Transfer Completion Chaining Example ................................................................. 833-19 Single Large Block Transfer Example ................................................................................... 843-20 Smaller Packet Data Transfers Example ................................................................................ 844-1 Channel Options Parameter (OPT) ...................................................................................... 874-2 Channel Source Address Parameter (SRC) ............................................................................ 894-3 A Count/B Count Parameter (A_B_CNT) ............................................................................... 894-4 Channel Destination Address Parameter (DST) ....................................................................... 904-5 Source B Index/Destination B Index Parameter (SRC_DST_BIDX) ................................................. 904-6 Link Address/B Count Reload Parameter (LINK_BCNTRLD) ........................................................ 914-7 Source C Index/Destination C Index Parameter (SRC_DST_CIDX) ................................................ 924-8 C Count Parameter (CCNT) .............................................................................................. 924-9 Peripheral ID Register (PID) .............................................................................................. 974-10 EDMA3CC Configuration Register (CCCFG) ........................................................................... 974-11 QDMA Channel Map nRegisters (QCHMAP n)........................................................................ 994-12 DMA Channel Queue Number Registers (DMAQNUM n)............................................................ 1004-13 QDMA Channel Queue Number Register (QDMAQNUM) .......................................................... 1014-14 Queue Priority Register (QUEPRI) ..................................................................................... 1024-15 Event Missed Register (EMR) ........................................................................................... 1034-16 Event Missed Register High (EMRH) .................................................................................. 1034-17 Event Missed Clear Register (EMCR) ................................................................................. 1044-18 Event Missed Clear Register High (EMCRH) ......................................................................... 104
6List of Figures SPRUG34 – November 2008Submit Documentation Feedback

www.ti.com
4-19 QDMA Event Missed Register (QEMR) ................................................................................ 1054-20 QDMA Event Missed Clear Register (QEMCR) ...................................................................... 1064-21 EDMA3CC Error Register (CCERR) ................................................................................... 1074-22 EDMA3CC Error Clear Register (CCERRCLR) ....................................................................... 1084-23 Error Evaluation Register (EEVAL) ..................................................................................... 1094-24 DMA Region Access Enable Register for Region m(DRAE m)..................................................... 1104-25 DMA Region Access Enable High Register for Region m(DRAEH m)............................................ 1104-26 QDMA Region Access Enable for Region m(QRAE m)............................................................. 1114-27 Event Queue Entry Registers (Q xEy).................................................................................. 1124-28 Queue nStatus Register (QSTAT n)................................................................................... 1134-29 Queue Watermark Threshold A Register (QWMTHRA) ............................................................. 1144-30 EDMA3CC Status Register (CCSTAT) ................................................................................ 1154-31 Event Register (ER) ...................................................................................................... 1174-32 Event Register High (ERH) .............................................................................................. 1174-33 Event Clear Register (ECR) ............................................................................................. 1184-34 Event Clear Register High (ECRH) ..................................................................................... 1184-35 Event Set Register (ESR)................................................................................................ 1194-36 Event Set Register High (ESRH) ....................................................................................... 1204-37 Chained Event Register (CER) ......................................................................................... 1214-38 Chained Event Register High (CERH) ................................................................................. 1214-39 Event Enable Register (EER) ........................................................................................... 1224-40 Event Enable Register High (EERH) ................................................................................... 1224-41 Event Enable Clear Register (EECR) .................................................................................. 1234-42 Event Enable Clear Register High (EECRH) .......................................................................... 1234-43 Event Enable Set Register (EESR) .................................................................................... 1244-44 Event Enable Set Register High (EESRH) ............................................................................ 1244-45 Secondary Event Register (SER) ....................................................................................... 1254-46 Secondary Event Register High (SERH) .............................................................................. 1264-47 Secondary Event Clear Register (SECR) ............................................................................. 1264-48 Secondary Event Clear Register High (SECRH) ..................................................................... 1274-49 Interrupt Enable Register (IER) ......................................................................................... 1284-50 Interrupt Enable Register High (IERH) ................................................................................. 1284-51 Interrupt Enable Clear Register (IECR) ................................................................................ 1294-52 Interrupt Enable Clear Register High (IECRH) ........................................................................ 1294-53 Interrupt Enable Set Register (IESR) .................................................................................. 1304-54 Interrupt Enable Set Register High (IESRH) .......................................................................... 1304-55 Interrupt Pending Register (IPR) ........................................................................................ 1314-56 Interrupt Pending Register High (IPRH) ............................................................................... 1314-57 Interrupt Clear Register (ICR) ........................................................................................... 1324-58 Interrupt Clear Register High (ICRH) ................................................................................... 1324-59 Interrupt Evaluate Register (IEVAL) .................................................................................... 1334-60 QDMA Event Register (QER) ........................................................................................... 1344-61 QDMA Event Enable Register (QEER) ................................................................................ 1354-62 QDMA Event Enable Clear Register (QEECR) ....................................................................... 1364-63 QDMA Event Enable Set Register (QEESR) ......................................................................... 1374-64 QDMA Secondary Event Register (QSER) ............................................................................ 1384-65 QDMA Secondary Event Clear Register (QSECR) .................................................................. 1394-66 Peripheral ID Register (PID)............................................................................................. 1414-67 EDMA3TC Configuration Register (TCCFG) .......................................................................... 1424-68 EDMA3TC Channel Status Register (TCSTAT) ...................................................................... 1434-69 Error Status Register (ERRSTAT) ...................................................................................... 1444-70 Error Enable Register (ERREN) ........................................................................................ 1454-71 Error Clear Register (ERRCLR) ........................................................................................ 146
SPRUG34 – November 2008 List of Figures 7Submit Documentation Feedback

www.ti.com
4-72 Error Details Register (ERRDET) ....................................................................................... 1474-73 Error Interrupt Command Register (ERRCMD) ....................................................................... 1484-74 Read Rate Register (RDRATE) ......................................................................................... 1494-75 Source Active Options Register (SAOPT) ............................................................................. 1504-76 Source Active Source Address Register (SASRC) ................................................................... 1514-77 Source Active Count Register (SACNT) ............................................................................... 1514-78 Source Active Destination Address Register (SADST) .............................................................. 1524-79 Source Active Source B-Dimension Index Register (SABIDX) ..................................................... 1524-80 Source Active Memory Protection Proxy Register (SAMPPRXY) .................................................. 1534-81 Source Active Count Reload Register (SACNTRLD) ................................................................ 1544-82 Source Active Source Address B-Reference Register (SASRCBREF) ............................................ 1544-83 Source Active Destination Address B-Reference Register (SADSTBREF) ....................................... 1554-84 Destination FIFO Options Register (DFOPT n)........................................................................ 1564-85 Destination FIFO Source Address Register (DFSRC n).............................................................. 1574-86 Destination FIFO Count Register (DFCNT n).......................................................................... 1584-87 Destination FIFO Destination Address Register (DFDST n)......................................................... 1594-88 Destination FIFO B-Index Register (DFBIDX n)....................................................................... 1594-89 Destination FIFO Memory Protection Proxy Register (DFMPPRXY n)............................................. 1604-90 Destination FIFO Count Reload Register (DFCNTRLD n)........................................................... 1614-91 Destination FIFO Source Address B-Reference Register (DFSRCBREF n)...................................... 1614-92 Destination FIFO Destination Address B-Reference Register (DFDSTBREF n).................................. 162
List of Figures8 SPRUG34 – November 2008Submit Documentation Feedback

www.ti.com
List of Tables
2-1 EDMA3 Parameter RAM Contents ....................................................................................... 282-2 EDMA3 Channel Parameter Description ................................................................................ 302-3 Dummy and Null Transfer Request ...................................................................................... 332-4 Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy PaRAM Set) ....................................... 342-5 EDMA3 Channel Synchronization Events ............................................................................... 382-6 Expected Number of Transfers for Non-Null Transfer ................................................................. 422-7 EDMA3 DMA Channel to PaRAM Mapping ............................................................................ 442-8 Shadow Region Registers ................................................................................................ 462-9 EDMA3 Shadow Regions ................................................................................................. 472-10 Chain Event Triggers ...................................................................................................... 482-11 EDMA3 Transfer Completion Interrupts ................................................................................. 492-12 EDMA3 Error Interrupts ................................................................................................... 492-13 Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping ................................................... 502-14 Number of Interrupts ....................................................................................................... 502-15 Read/Write Command Optimization Rules.............................................................................. 582-16 EDMA3 Transfer Controller Configurations ............................................................................. 594-1 EDMA3 Channel Controller (EDMA3CC) Parameter RAM (PaRAM) Entries ...................................... 864-2 Channel Options Parameters (OPT) Field Descriptions .............................................................. 874-3 Channel Source Address Parameter (SRC) Field Descriptions ...................................................... 894-4 A Count/B Count Parameter (A_B_CNT) Field Descriptions ......................................................... 894-5 Channel Destination Address Parameter (DST) Field Descriptions ................................................. 904-6 Source B Index/Destination B Index Parameter (SRC_DST_BIDX) Field Descriptions .......................... 904-7 Link Address/B Count Reload Parameter (LINK_BCNTRLD) Field Descriptions .................................. 914-8 Source C Index/Destination C Index Parameter (SRC_DST_CIDX) Field Descriptions .......................... 924-9 C Count Parameter (CCNT) Field Descriptions ........................................................................ 924-10 EDMACC Registers ........................................................................................................ 934-11 Peripheral ID Register (PID) Field Descriptions ........................................................................ 974-12 EDMA3CC Configuration Register (CCCFG) Field Descriptions .................................................... 984-13 QDMA Channel Map nRegisters (QCHMAP n) Field Descriptions .................................................. 994-14 DMA Channel Queue Number Registers (DMAQNUM n) Field Descriptions ..................................... 1004-15 Bits in DMAQNUM n...................................................................................................... 1004-16 QDMA Channel Queue Number Register (QDMAQNUM) Field Descriptions .................................... 1014-17 Queue Priority Register (QUEPRI) Field Descriptions ............................................................... 1024-18 Event Missed Register (EMR) Field Descriptions .................................................................... 1034-19 Event Missed Register High (EMRH) Field Descriptions ............................................................ 1034-20 Event Missed Clear Register (EMCR) Field Descriptions ........................................................... 1044-21 Event Missed Clear Register High (EMCRH) Field Descriptions ................................................... 1044-22 QDMA Event Missed Register (QEMR) Field Descriptions ......................................................... 1054-23 QDMA Event Missed Clear Register (QEMCR) Field Descriptions ................................................ 1064-24 EDMA3CC Error Register (CCERR) Field Descriptions ............................................................. 1074-25 EDMA3CC Error Clear Register (CCERRCLR) Field Descriptions ................................................ 1084-26 Error Evaluation Register (EEVAL) Field Descriptions .............................................................. 1094-27 DMA Region Access Enable Registers for Region m(DRAE m/DRAEH m) Field Descriptions ................. 1104-28 QDMA Region Access Enable for Region m(QRAE m) Field Descriptions ....................................... 1114-29 Event Queue Entry Registers (Q xEy) Field Descriptions ............................................................ 1124-30 Queue nStatus Register (QSTAT n) Field Descriptions ............................................................. 1134-31 Queue Watermark Threshold A Register (QWMTHRA) Field Descriptions ....................................... 1144-32 EDMA3CC Status Register (CCSTAT) Field Descriptions .......................................................... 1154-33 Event Register (ER) Field Descriptions ................................................................................ 117
SPRUG34 – November 2008 List of Tables 9Submit Documentation Feedback

www.ti.com
4-34 Event Register High (ERH) Field Descriptions ........................................................................ 1174-35 Event Clear Register (ECR) Field Descriptions ....................................................................... 1184-36 Event Clear Register High (ECRH) Field Descriptions .............................................................. 1184-37 Event Set Register (ESR) Field Descriptions ......................................................................... 1194-38 Event Set Register High (ESRH) Field Descriptions ................................................................. 1204-39 Chained Event Register (CER) Field Descriptions ................................................................... 1214-40 Chained Event Register High (CERH) Field Descriptions ........................................................... 1214-41 Event Enable Register (EER) Field Descriptions ..................................................................... 1224-42 Event Enable Register High (EERH) Field Descriptions ............................................................. 1234-43 Event Enable Clear Register (EECR) Field Descriptions ............................................................ 1234-44 Event Enable Clear Register High (EECRH) Field Descriptions ................................................... 1244-45 Event Enable Set Register (EESR) Field Descriptions ............................................................. 1244-46 Event Enable Set Register High (EESRH) Field Descriptions ...................................................... 1254-47 Secondary Event Register (SER) Field Descriptions ................................................................ 1254-48 Secondary Event Register High (SERH) Field Descriptions ........................................................ 1264-49 Secondary Event Clear Register (SECR) Field Descriptions ....................................................... 1264-50 Secondary Event Clear Register High (SECRH) Field Descriptions ............................................... 1274-51 Interrupt Enable Register (IER) Field Descriptions ................................................................... 1284-52 Interrupt Enable Register High (IERH) Field Descriptions .......................................................... 1284-53 Interrupt Enable Clear Register (IECR) Field Descriptions .......................................................... 1294-54 Interrupt Enable Clear Register High (IECRH) Field Descriptions ................................................. 1294-55 Interrupt Enable Set Register (IESR) Field Descriptions ............................................................ 1304-56 Interrupt Enable Set Register High (IESRH) Field Descriptions .................................................... 1304-57 Interrupt Pending Register (IPR) Field Descriptions ................................................................. 1314-58 Interrupt Pending Register High (IPRH) Field Descriptions ......................................................... 1314-59 Interrupt Clear Register (ICR) Field Descriptions ..................................................................... 1324-60 Interrupt Clear Register High (ICRH) Field Descriptions ............................................................ 1324-61 Interrupt Evaluate Register (IEVAL) Field Descriptions ............................................................. 1334-62 QDMA Event Register (QER) Field Descriptions ..................................................................... 1344-63 QDMA Event Enable Register (QEER) Field Descriptions .......................................................... 1354-64 QDMA Event Enable Clear Register (QEECR) Field Descriptions ................................................. 1364-65 QDMA Event Enable Set Register (QEESR) Field Descriptions ................................................... 1374-66 QDMA Secondary Event Register (QSER) Field Descriptions ..................................................... 1384-67 QDMA Secondary Event Clear Register (QSECR) Field Descriptions ............................................ 1394-68 EDMA3 Transfer Controller Registers ................................................................................. 1404-69 Peripheral ID Register (PID) Field Descriptions ...................................................................... 1414-70 EDMA3TC Configuration Register (TCCFG) Field Descriptions ................................................... 1424-71 EDMA3TC Channel Status Register (TCSTAT) Field Descriptions ................................................ 1434-72 Error Status Register (ERRSTAT) Field Descriptions ............................................................... 1444-73 Error Enable Register (ERREN) Field Descriptions .................................................................. 1454-74 Error Clear Register (ERRCLR) Field Descriptions .................................................................. 1464-75 Error Details Register (ERRDET) Field Descriptions ................................................................ 1474-76 Error Interrupt Command Register (ERRCMD) Field Descriptions ................................................. 1484-77 Read Rate Register (RDRATE) Field Descriptions .................................................................. 1494-78 Source Active Options Register (SAOPT) Field Descriptions ....................................................... 1504-79 Source Active Source Address Register (SASRC) Field Descriptions ............................................ 1514-80 Source Active Count Register (SACNT) Field Descriptions ......................................................... 1514-81 Source Active Destination Address Register (SADST) Field Descriptions ........................................ 1524-82 Source Active Source B-Dimension Index Register (SABIDX) Field Descriptions ............................... 1524-83 Source Active Memory Protection Proxy Register (SAMPPRXY) Field Descriptions ............................ 1534-84 Source Active Count Reload Register (SACNTRLD) Field Descriptions .......................................... 154
10 List of Tables SPRUG34 – November 2008Submit Documentation Feedback

Other manuals for TMS320DM357

Table of contents

Other Texas Instruments Microcontroller manuals

Texas Instruments

Texas Instruments MSP430F533x User manual

Texas Instruments

Texas Instruments Hercules RM48 User manual

Texas Instruments

Texas Instruments MSPM0G310 Series User manual

Texas Instruments

Texas Instruments CC3220 User manual

Texas Instruments

Texas Instruments TM4C1294NCPDT User manual

Texas Instruments

Texas Instruments Chipcon Products CC1110DK Programming manual

Texas Instruments

Texas Instruments Silicon Errata TMS320F28379S User manual

Texas Instruments

Texas Instruments MSP430F6726 User manual

Texas Instruments

Texas Instruments Serial Programming Adapter MSP430 User manual

Texas Instruments

Texas Instruments LaunchPad CC2650 User manual

Texas Instruments

Texas Instruments CC2510 Programming manual

Texas Instruments

Texas Instruments CC13 Series User manual

Texas Instruments

Texas Instruments Vision SDK Linux User manual

Texas Instruments

Texas Instruments LaunchPad CC1312PSIP User manual

Texas Instruments

Texas Instruments CC2540 User manual

Texas Instruments

Texas Instruments TPS6381 EVM Series User manual

Texas Instruments

Texas Instruments TMS570LS User manual

Texas Instruments

Texas Instruments SimpleLink CC3200 Wi-Fi Manual

Texas Instruments

Texas Instruments REF70EVM User manual

Texas Instruments

Texas Instruments MSP430F67781 User manual

Texas Instruments

Texas Instruments LaunchPad LP-CC1352P7-1 User manual

Texas Instruments

Texas Instruments CC2430ZDK User manual

Texas Instruments

Texas Instruments MSP430F67771 User manual

Texas Instruments

Texas Instruments MSP430F6749 User manual

Popular Microcontroller manuals by other brands

AMS

AMS AS7261 Demo Kit user guide

Novatek

Novatek NT6861 manual

Espressif Systems

Espressif Systems ESP8266 SDK AT Instruction Set

Nuvoton

Nuvoton ISD61S00 ChipCorder Design guide

STMicrolectronics

STMicrolectronics ST7 Assembler Linker user manual

Lantronix

Lantronix Intrinsyc Open-Q 865XR SOM user guide

NEC

NEC 78GK0S/K 1+ Series Application note

Mikroe

Mikroe SEMITECH N-PLC Click Application note

Intel

Intel Agilex user guide

Cypress

Cypress CY4607 HX2VL quick start guide

DIGITAL-LOGIC

DIGITAL-LOGIC MICROSPACE manual

CYPRES

CYPRES CY14NVSRAMKIT-001 user guide

Espressif Systems

Espressif Systems ESP8266EX Programming guide

Abov

Abov AC33M8128L user manual

Laird

Laird BL654PA user guide

Silicon Laboratories

Silicon Laboratories C8051F800 user guide

Energy micro

Energy micro EFM32 Giant Gecko Starter Kit user manual

Mikroe

Mikroe click Proximity 2 manual