Texas Instruments TAS5805M User manual

System

Processor

Digital

Audio

Source

ADR/FAULT

PDN

SDOUT

SDA

SCL

SDIN

SCLK (BCLK)

LRCLK

BST_A+

OUT_A+

BST_A-

OUT_A-

BST_B+

OUT_B+

BST_B-

OUT_B-

Speaker

L Channel Speaker

R Channel

DVDD

Product

Folder

Order

Now

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Software

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Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TAS5805M

SLASEH5A –MAY 2018–REVISED JULY 2018

TAS5805M 23-W, Inductor-Less, Digital Input, Stereo, Closed-Loop Class-D Audio

Amplifier with Enhanced Processing and Low Idle Power Dissipation

1 Features

1• Supports Multiple Output Configurations

– 2 × 23 W in 2.0 Mode (8-Ω, 21 V, THD+N=1%)

– 45 W in Mono Mode (4-Ω, 21 V, THD+N=1%)

• Excellent Audio Performance

– THD+N ≤0.03% at 1 W, 1 kHz, PVDD = 12 V

– SNR ≥107 dB (A-weighted), Noise Level < 40

µVRMS

• Low Quiescent Current with Hybrid Modulation

– 16.5 mA at PVDD = 13.5 V , 22 µH + 0.68 µF

Filter

• Flexible Power Supply Configurations

– PVDD: 4.5 V to 26.4 V

– DVDD and I/O: 1.8 V or 3.3 V

• Flexible Audio I/O

– I2S, LJ, RJ, TDM, 3-Wire Digital Audio

Interface (No MCLK Required)

– Supports 32, 44.1, 48, 88.2, 96 kHz Sample

Rates

– SDOUT for Audio Monitoring, Sub-Channel or

Echo Cancellation

• Enhanced Audio Processing

– Multi-Band Advanced DRC and AGL

– 2×15 BQs, Thermal Foldback, DC Blocking

– Input Mixer, Output Crossbar, Level Meter

– 5 BQs + 1 Band DRC +THD Manager for the

Subwoofer Channel

• Integrated Self-Protection

– Adjacent Pin to Pin Short Without Device

Damage

– Over-Current Error (OCE)

– Over-Temperature Warning (OTW)

– Over-Temperature Error (OTE)

– Under/Over-Voltage Lock-out (UVLO/OVLO)

• Easy System Integration

– I2C Software Control

– Reduced Solution Size

– Fewer Passives Required Compared to

Open-Loop Devices

– Inductor-less Operation (Ferrite Bead) for

most cases where PVDD ≤14V

2 Applications

• LCD TV, OLED TV

• Wireless Speaker, Smart Speaker with Voice

Assistant

• Soundbar, Wired Speaker , Bookshelf Stereo

System

• Desktop PC, Notebook PC

• AV Receiver, Smart Home and IoT Appliance

3 Description

The TAS5805M is a high-efficiency, stereo, closed-

loop Class-D amplifier offering a cost effective digital-

input solution with low power dissipation and sound

enrichment. The device’s integrated audio processor

and 96 kHz architecture supports advanced audio

process flow, including SRC, 15 BQs per channel,

volume control, audio mixing, 3-band 4th order DRC,

full-band AGL, THD managing and level meter.

Featuring TI's proprietary Hybrid Modulation scheme,

the TAS5805M consumes very-low quiescent current

(<16.5 mA at 13.5V PVDD), extending battery life in

portable audio applications. With advanced EMI

suppression technology, designers can leverage

inexpensive ferrite bead filters to reduced board

space and system cost.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

TAS5805M TSSOP (28) PWP 9.7 mm × 4.4 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Block Diagram

TAS5805M

SLASEH5A –MAY 2018–REVISED JULY 2018

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Product Folder Links: TAS5805M

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Device Comparison Table..................................... 3

6 Pin Configuration and Functions......................... 3

7 Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings ............................................................ 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Timing Requirements ............................................... 9

7.7 Typical Characteristics............................................ 10

8 Parameter Measurement Information ................ 19

9 Detailed Description............................................ 20

9.1 Overview................................................................. 20

9.2 Functional Block Diagram....................................... 20

9.3 Feature Description................................................. 21

9.4 Device Functional Modes........................................ 25

9.5 Programming and Control....................................... 30

9.6 Register Maps......................................................... 34

10 Application and Implementation........................ 65

10.1 Application Information.......................................... 65

10.2 Typical Applications ............................................. 65

11 Power Supply Recommendations ..................... 74

11.1 DVDD Supply........................................................ 74

11.2 PVDD Supply........................................................ 74

12 Layout................................................................... 76

12.1 Layout Guidelines ................................................. 76

12.2 Layout Example .................................................... 78

13 Device and Documentation Support................. 79

13.1 Device Support...................................................... 79

13.2 Receiving Notification of Documentation Updates 79

13.3 Community Resources.......................................... 80

13.4 Trademarks........................................................... 80

13.5 Electrostatic Discharge Caution............................ 80

13.6 Glossary................................................................ 80

14 Mechanical, Packaging, and Orderable

Information........................................................... 80

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (May 2018) to Revision A Page

• Released as Production Data................................................................................................................................................. 1

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5 Device Comparison Table

ORDERABLE PART

NUMBER RECOMMENDED

PVDD RANGE Audio Process Flows RDS(ON)

TAS5805M 4.5 V to 26.4 V Enhanced Audio Process Flows with ROM Fixed 180 mΩ

TAS5707/TAS5711 8 V to 26 V Basic Audio Process Flow with ROM Fixed 180 mΩ

TAS5825M 4.5 V to 26.4 V Flexible Advanced Audio Process Flows with Smart-Amp

Features 90 mΩ

6 Pin Configuration and Functions

PWP Package

28-Pin TSSOP

(1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P =

Power, G = Ground (0 V)

Pin Functions

PIN TYPE(1) DESCRIPTION

NAME NO.

DGND 1, 5 P Digital ground

DVDD 2 P 3.3-V or 1.8-V digital power supply

VR_DIG 4 P Internally regulated 1.5-V digital supply voltage. This pin must not be used to drive external devices

ADR/FAULT 3 DI/O Different I2C device address can be set by selecting different pull up resistor to DVDD, see Table 4 for details.

This pin can be programed by Register 0x60h and 0x61h after Power up bit. In this mode, the ADR/FAULT Is

redefined as FAULT

LRCLK 6 DI Word select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ and RJ, this

corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync

boundary.

SCLK 7 DI Bit clock for the digital signal that is active on the input data line of the serial data port.

SDIN 8 DI Data line to the serial data port

SDOUT 9 DO Serial Audio data output. The source data can be Pre-DSP or Post DSP data, by setting the register 0x30h.

SDA 10 DI/O I2C serial control data interface input/output

TAS5805M

SLASEH5A –MAY 2018–REVISED JULY 2018

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Pin Functions (continued)

PIN TYPE(1) DESCRIPTION

NAME NO.

SCL 11 DI I2C serial control clock input

PDN 12 DI Power Down, active-low.PDN place the amplifier in Shutdown, turn off all internal regulators. Low, Power Down

Device; High, Enable Device.

AVDD 13 P Internally regulated 5-V analog supply voltage. This pin must not be used to drive external devices

AGND 14 P Analog ground

PVDD 15,16,27,

28 P PVDD voltage input

PGND 19,24 P Ground reference for power device circuitry. Connect this pin to system ground.

OUT_A+ 26 O Positive pin for differential speaker amplifier output A+

BST_A+ 25 P Connection point for the OUT_A+ bootstrap capacitor which is used to create a power supply for the high-side

gate drive for OUT_A+

OUT_A- 23 O Negative pin for differential speaker amplifier output A-

BST_A- 22 P Connection point for the OUT_A- bootstrap capacitor which is used to create a power supply for the high-side gate

drive for OUT_A-

BST_B- 21 P Connection point for the OUT_B- bootstrap capacitor which is used to create a power supply for the high-side gate

drive for OUT_B-

OUT_B- 20 O Negative pin for differential speaker amplifier output B

BST_B+ 18 P Connection point for the OUT_B+ bootstrap capacitor which is used to create a power supply for the high-side

gate drive for OUT_B+

OUT_B+ 17 O Positive pin for differential speaker amplifier output B+

PowerPAD™ P Connect to the system Ground

TAS5805M

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SLASEH5A –MAY 2018–REVISED JULY 2018

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) DVDD referenced digital pins include: ADR/FAULT, LRCLK, SCLK, SCL, SDA, SDIN,PDN

7 Specifications

7.1 Absolute Maximum Ratings

Free-air room temperature 25°C (unless otherwise noted) (1)

MIN MAX UNIT

DVDD Low-voltage digital supply –0.3 3.9 V

PVDD PVDD supply –0.3 30 V

VI(DigIn) DVDD referenced digital inputs(2) –0.5 VDVDD + 0.5 V

VI(SPK_OUTxx) Voltage at speaker output pins –0.3 32 V

TAAmbient operating temperature –25 85 °C

Tstg Storage temperature –40 125 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V

Charged-device model (CDM), per JEDEC specification JESD22-

C101(2) ±500

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT

V(POWER) Power supply inputs DVDD 1.62 3.63 V

PVDD 4.5 26.4

RSPK Minimum speaker load BTL Mode (4.5V≤PVDD≤16V) 3.2 Ω

BTL Mode (16V<PVDD≤24V) 4.8 Ω

RSPK Minimum speaker load PBTL Mode (4.5V≤PVDD≤16V) 1.6 Ω

PBLT Mode (16V<PVDD≤24V) 2.4 Ω

LOUT Minimum inductor value in LC filter under short-circuit condition 1 4.7 µH

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.4 Thermal Information

THERMAL METRIC(1)

TAS5805M

TSSOP (PWP)

28 PINS UNIT

JEDEC

STANDARD

2-LAYER PCB

JEDEC

STANDARD

4-LAYER PCB

TAS5805MEVM-4

4-LAYER PCB

RθJA Junction-to-ambient thermal resistance N/A 29.1 24 °C/W

RθJC(top) Junction-to-case (top) thermal resistance N/A 21.8 N/A °C/W

RθJB Junction-to-board thermal resistance N/A 8.2 N/A °C/W

ψJT Junction-to-top characterization parameter N/A 0.3 1.5 °C/W

ψJB Junction-to-board characterization parameter N/A 8.1 7.6 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 2.2 N/A °C/W

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7.5 Electrical Characteristics

Free-air room temperature 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DIGITAL I/O

|IIH| Input logic high current level

for DVDD referenced digital

input pins VIN(DigIn) = VDVDD 10 µA

|IIL| Input logic low current level

for DVDD referenced digital

input pins VIN(DigIn) = 0 V –10 µA

VIH(Digin) Input logic high threshold for

DVDD referenced digital

inputs 70% VDVDD

VIL(Digin) Input logic low threshold for

DVDD referenced digital

inputs 30% VDVDD

VOH(Digin) Output logic high voltage

level IOH = 2 mA 80% VDVDD

VOL(Digin) Output logic low voltage level IOH = –2 mA 20% VDVDD

I2C CONTROL PORT

CL(I2C) Allowable load capacitance

for each I2C line 400 pF

fSCL(fast) Support SCL frequency No wait states, fast mode 400 kHz

fSCL(slow) Support SCL frequency No wait states, slow mode 100 kHz

SERIAL AUDIO PORT

tDLY Required LRCLK/FS to SCLK

rising edge delay 5 ns

DSCLK Allowable SCLK duty cycle 40% 60%

fSSupported input sample rates 32 96 kHz

fSCLK Supported SCLK frequencies 32 64 fS

fSCLK SCLK frequency 24.576 MHz

SPEAKER AMPLIFIER (ALL OUTPUT CONFIGURATIONS)