Texas Instruments MSP430F22x4 Series User manual

MSP430F22x2

MSP430F22x4

www.ti.com

SLAS504G –JULY 2006–REVISED AUGUST 2012

MIXED SIGNAL MICROCONTROLLER

1FEATURES

23• Low Supply Voltage Range: 1.8 V to 3.6 V • Two Configurable Operational Amplifiers

(MSP430F22x4 Only)

• Ultra-Low Power Consumption • Brownout Detector

– Active Mode: 270 µA at 1 MHz, 2.2 V • Serial Onboard Programming, No External

– Standby Mode: 0.7 µA Programming Voltage Needed, Programmable

– Off Mode (RAM Retention): 0.1 µA Code Protection by Security Fuse

• Ultra-Fast Wake-Up From Standby Mode in • Bootstrap Loader

Less Than 1 µs • On-Chip Emulation Module

• 16-Bit RISC Architecture, 62.5-ns Instruction • Family Members Include:

Cycle Time – MSP430F2232

• Basic Clock Module Configurations – 8KB + 256B Flash Memory

– Internal Frequencies up to 16 MHz With

Four Calibrated Frequencies to ±1% – 512B RAM

– Internal Very-Low-Power Low-Frequency – MSP430F2252

Oscillator – 16KB + 256B Flash Memory

– 32-kHz Crystal – 512B RAM

– High-Frequency (HF) Crystal up to 16 MHz – MSP430F2272

– Resonator – 32KB + 256B Flash Memory

– External Digital Clock Source – 1KB RAM

– External Resistor – MSP430F2234

• 16-Bit Timer_A With Three Capture/Compare – 8KB + 256B Flash Memory

Registers – 512B RAM

• 16-Bit Timer_B With Three Capture/Compare – MSP430F2254

Registers – 16KB + 256B Flash Memory

• Universal Serial Communication Interface – 512B RAM

– Enhanced UART Supporting Auto-Baudrate – MSP430F2274

Detection (LIN) – 32KB + 256B Flash Memory

– IrDA Encoder and Decoder – 1KB RAM

– Synchronous SPI • Available in a 38-Pin Thin Shrink Small-Outline

– I2C™ Package (TSSOP) (DA), 40-Pin QFN Package

• 10-Bit 200-ksps Analog-to-Digital (A/D) (RHA), and 49-Pin Ball Grid Array Package

Converter With Internal Reference, Sample- (YFF) (See Table 1)

and-Hold, Autoscan, and Data Transfer • For Complete Module Descriptions, See the

Controller MSP430x2xx Family User's Guide (SLAU144)

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2MSP430 is a trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

MSP430F22x2

MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION

The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consist of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low-power

modes is optimized to achieve extended battery life in portable measurement applications. The device features a

powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.

The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.

The MSP430F22x4/MSP430F22x2 series is an ultra-low-power mixed signal microcontroller with two built-in 16-

bit timers, a universal serial communication interface, 10-bit A/D converter with integrated reference and data

transfer controller (DTC), two general-purpose operational amplifiers in the MSP430F22x4 devices, and 32 I/O

pins.

Typical applications include sensor systems that capture analog signals, convert them to digital values, and then

process the data for display or for transmission to a host system. Stand-alone radio-frequency (RF) sensor front

ends are another area of application.

Table 1. Available Options

PACKAGED DEVICES(1)(2)

TAPLASTIC 49-PIN BGA PLASTIC 38-PIN TSSOP PLASTIC 40-PIN QFN

(YFF) (DA) (RHA)

MSP430F2232IYFF MSP430F2232IDA MSP430F2232IRHA

MSP430F2252IYFF MSP430F2252IDA MSP430F2252IRHA

MSP430F2272IYFF MSP430F2272IDA MSP430F2272IRHA

-40°C to 85°C MSP430F2234IYFF MSP430F2234IDA MSP430F2234IRHA

MSP430F2254IYFF MSP430F2254IDA MSP430F2254IRHA

MSP430F2274IYFF MSP430F2274IDA MSP430F2274IRHA

MSP430F2232TDA MSP430F2232TRHA

MSP430F2252TDA MSP430F2252TRHA

MSP430F2272TDA MSP430F2272TRHA

-40°C to 105°C MSP430F2234TDA MSP430F2234TRHA

MSP430F2254TDA MSP430F2254TRHA

MSP430F2274TDA MSP430F2274TRHA

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

Development Tool Support

All MSP430™ microcontrollers include an Embedded Emulation Module (EEM) that allows advanced debugging

and programming through easy-to-use development tools. Recommended hardware options include:

• Debugging and Programming Interface

– MSP-FET430UIF (USB)

– MSP-FET430PIF (Parallel Port)

• Debugging and Programming Interface with Target Board

– MSP-FET430U38 (DA package)

• Production Programmer

– MSP-GANG430

1TEST/SBWTCK

2DVCC

3P2.5/ROSC

XOUT/P2.7 5

XIN/P2.6 6

RST/NMI/SBWTDIO 7

P2.0/ACLK/A0/OA0I0 8

P2.1/TAINCLK/SMCLK/A1/OA0O 9

P2.2/TA0/A2/OA0I1 10

P3.0/UCB0STE/UCA0CLK/A5 11

P3.1/UCB0SIMO/UCB0SDA 12

P3.2/UCB0SOMI/UCB0SCL 13

P3.3/UCB0CLK/UCA0STE 14

P4.0/TB0

P4.1/TB1

P4.2/TB2

P4.3/TB0/A12/OA0O

18 P4.4/TB1/A13/OA1O

38 P1.7/TA2/TDO/TDI

37 P1.6/TA1/TDI

36 P1.5/TA0/TMS

35 P1.4/SMCLK/TCK

34 P1.3/TA2

33 P1.2/TA1

32 P1.1/TA0

31 P1.0/TACLK/ADC10CLK

30 P2.4/TA2/A4/VREF+/VeREF+/OA1I0

29 P2.3/TA1/A3/VREF−/VeREF−/OA1I1/OA1O

28 P3.7/A7/OA1I2

27 P3.6/A6/OA0I2

26 P3.5/UCA0RXD/UCA0SOMI

25 P3.4/UCA0TXD/UCA0SIMO

23AVCC

AVSS

P4.7/TBCLK

P4.6/TBOUTH/A15/OA1I3

DVSS

P4.5/TB2/A14/OA0I3

1TEST/SBWTCK

2DVCC

3P2.5/ROSC

XOUT/P2.7 5

XIN/P2.6 6

RST/NMI/SBWTDIO 7

P2.0/ACLK/A0 8

P2.1/TAINCLK/SMCLK/A1 9

P2.2/TA0/A2 10

P3.0/UCB0STE/UCA0CLK/A5 11

P3.1/UCB0SIMO/UCB0SDA 12

P3.2/UCB0SOMI/UCB0SCL 13

P3.3/UCB0CLK/UCA0STE 14

P4.0/TB0

P4.1/TB1

P4.2/TB2

P4.3/TB0/A12

18 P4.4/TB1/A13

38 P1.7/TA2/TDO/TDI

37 P1.6/TA1/TDI

36 P1.5/TA0/TMS

35 P1.4/SMCLK/TCK

34 P1.3/TA2

33 P1.2/TA1

32 P1.1/TA0

31 P1.0/TACLK/ADC10CLK

30 P2.4/TA2/A4/VREF+/VeREF+

29 P2.3/TA1/A3/VREF−/VeREF−

28 P3.7/A7

27 P3.6/A6

26 P3.5/UCA0RXD/UCA0SOMI

25 P3.4/UCA0TXD/UCA0SIMO

23AVCC

AVSS

P4.7/TBCLK

P4.6/TBOUTH/A15

DVSS

P4.5/TB2/A14

MSP430F22x2

MSP430F22x4

www.ti.com

SLAS504G –JULY 2006–REVISED AUGUST 2012

MSP430F22x2 Device Pinout, DA Package

MSP430F22x4 Device Pinout, DA Package

1DVSS

P1.5/TA0/TMS

P1.0/TACLK/ADC10CLK

P1.1/TA0

P1.2/TA1

P1.3/TA2

P1.4/SMCLK/TCK

P2.4/TA2/A4/VREF+/VeREF+

P2.5/ROSC

DVCC

TEST/SBWTCK

P1.6/TA1/TDI/TCLK

12 14 15 16 17 18 19

3839 37 36 35 34 33 32

XOUT/P2.7

XIN/P2.6

DVSS

RST/NMI/SBWTDIO

P2.0/ACLK/A0

P2.1/TAINCLK/SMCLK/A1

P2.2/TA0/A2

P3.0/UCB0STE/UCA0CLK/A5

P3.1/UCB0SIMO/UCB0SDA

DVCC

P1.7/TA2/TDO/TDI

P2.3/TA1/A3/VREF−/VeREF−

P3.7/A7

P3.6/A6

P3.5/UCA0RXD/UCA0SOMI

P3.4/UCA0TXD/UCA0SIMO

AVCC

AVSS

P3.2/UCB0SOMI/UCB0SCL

P3.3/UCB0CLK/UCA0STE

P4.0/TB0

P4.1/TB1

P4.2/TB2

P4.3/TB0/A12

P4.4/TB1/A13

P4.5/TB2/A14

P4.6/TBOUTH/A15

P4.7/TBCLK

MSP430F22x2

MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

www.ti.com

MSP430F22x2 Device Pinout, RHA Package

1DVSS

P1.5/TA0/TMS

P1.0/TACLK/ADC10CLK

P1.1/TA0

P1.2/TA1

P1.3/TA2

P1.4/SMCLK/TCK

P2.4/TA2/A4/VREF+/VeREF+/OA1I0

P2.5/ROSC

DVCC

TEST/SBWTCK

P1.6/TA1/TDI/TCLK

12 14 15 16 17 18 19

3839 37 36 35 34 33 32

XOUT/P2.7

XIN/P2.6

DVSS

RST/NMI/SBWTDIO

P2.0/ACLK/A0/OA0I0

P2.1/TAINCLK/SMCLK/A1/OA0O

P2.2/TA0/A2/OA0I1

P3.0/UCB0STE/UCA0CLK/A5

P3.1/UCB0SIMO/UCB0SDA

DVCC

P1.7/TA2/TDO/TDI

P2.3/TA1/A3/VREF−/VeREF−/OA1I1/OA1O

P3.7/A7/OA1I2

P3.6/A6/OA0I2

P3.5/UCA0RXD/UCA0SOMI

P3.4/UCA0TXD/UCA0SIMO

AVCC

AVSS

P3.2/UCB0SOMI/UCB0SCL

P3.3/UCB0CLK/UCA0STE

P4.0/TB0

P4.1/TB1

P4.2/TB2

P4.3/TB0/A12/OA0O

P4.4/TB1/A13/OA1O

P4.5/TB2/A14/OA0I3

P4.6/TBOUTH/A15/OA1I3

P4.7/TBCLK

MSP430F22x2

MSP430F22x4

www.ti.com

SLAS504G –JULY 2006–REVISED AUGUST 2012

MSP430F22x4 Device Pinout, RHA Package

A1 A2 A4A3 A5 A6 A7

TOP VIEW

B1 B2 B4B3 B5 B6 B7

C1 C2 C4C3 C5 C6 C7

D1 D2 D4D3 D5 D6 D7

E1 E2 E4E3 E5 E6 E7

F1 F2 F4F3 F5 F6 F7

G1 G2 G4G3 G5 G6 G7

MSP430F22x2

MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

www.ti.com

MSP430F22x4, MSP430F22x2 Device Pinout, YFF Package

Package Dimensions

The package dimensions for this YFF package are shown in Table 2. See the package drawing at the end of this

data sheet for more details.

Table 2. YFF Package Dimensions

PACKAGED DEVICES D E

MSP430F22x2 3.33 ± 0.03 mm 3.49 ± 0.03 mm

MSP430F22x4

Basic Clock

System+

RAM

1kB

512B

Brownout

Protection

RST/NMI

VCC VSS

MCLK

SMCLK

Watchdog

WDT+

15/16−Bit

Timer_A3

3 CC

Registers

16MHz

CPU

incl. 16

Registers

Emulation

(2BP)

XOUT

JTAG

Interface

Flash

32kB

16kB

8kB

ACLK

XIN

MDB

MAB

Spy−Bi Wire

Timer_B3

3 CC

Registers,

Shadow

Reg

USCI_A0:

UART/LIN,

IrDA, SPI

USCI_B0:

SPI, I2C

OA0, OA1

2 Op Amps

ADC10

10−Bit

Channels,

Autoscan,

DTC

Ports P1/P2

2x8 I/O

Interrupt

capability,

pull−up/down

resistors

Ports P3/P4

2x8 I/O

pull−up/down

resistors

P1.x/P2.x

2x8

P3.x/P4.x

2x8

Basic Clock

System+

RAM

1kB

512B

Brownout

Protection

RST/NMI

VCC VSS

MCLK

SMCLK

Watchdog

WDT+

15/16−Bit

Timer_A3

3 CC

Registers

16MHz

CPU

incl. 16

Registers

Emulation

(2BP)

XOUT

JTAG

Interface

Flash

32kB

16kB

8kB

ACLK

XIN

MDB

MAB

Spy−Bi Wire

Timer_B3

3 CC

Registers,

Shadow

Reg

USCI_A0:

UART/LIN,

IrDA, SPI

USCI_B0:

SPI, I2C

ADC10

10−Bit

Channels,

Autoscan,

DTC

Ports P1/P2

2x8 I/O

Interrupt

capability,

pull−up/down

resistors

Ports P3/P4

2x8 I/O

pull−up/down

resistors

P1.x/P2.x

2x8

P3.x/P4.x

2x8

MSP430F22x2

MSP430F22x4

www.ti.com

SLAS504G –JULY 2006–REVISED AUGUST 2012

MSP430F22x2 Functional Block Diagram

MSP430F22x4 Functional Block Diagram

MSP430F22x2

MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

www.ti.com

Table 3. Terminal Functions, MSP430F22x2

TERMINAL

NO. I/O DESCRIPTION

NAME YFF DA RHA

General-purpose digital I/O pin

P1.0/TACLK/ADC10CLK F2 31 29 I/O Timer_A, clock signal TACLK input

ADC10, conversion clock

General-purpose digital I/O pin

P1.1/TA0 G2 32 30 I/O Timer_A, capture: CCI0A input, compare: OUT0 output

BSL transmit

General-purpose digital I/O pin

P1.2/TA1 E2 33 31 I/O Timer_A, capture: CCI1A input, compare: OUT1 output

General-purpose digital I/O pin

P1.3/TA2 G1 34 32 I/O Timer_A, capture: CCI2A input, compare: OUT2 output

General-purpose digital I/O pin

P1.4/SMCLK/TCK F1 35 33 I/O SMCLK signal output

Test Clock input for device programming and test

General-purpose digital I/O pin

P1.5/TA0/TMS E1 36 34 I/O Timer_A, compare: OUT0 output

Test Mode Select input for device programming and test

General-purpose digital I/O pin

P1.6/TA1/TDI/TCLK E3 37 35 I/O Timer_A, compare: OUT1 output

Test Data Input or Test Clock Input for programming and test

General-purpose digital I/O pin

P1.7/TA2/TDO/TDI(1) D2 38 36 I/O Timer_A, compare: OUT2 output

Test Data Output or Test Data Input for programming and test

General-purpose digital I/O pin

P2.0/ACLK/A0 A4 8 6 I/O ACLK output

ADC10, analog input A0

General-purpose digital I/O pin

Timer_A, clock signal at INCLK

P2.1/TAINCLK/SMCLK/A1 B4 9 7 I/O SMCLK signal output

ADC10, analog input A1

General-purpose digital I/O pin

P2.2/TA0/A2 A5 10 8 I/O Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output

ADC10, analog input A2

General-purpose digital I/O pin

Timer_A, capture CCI1B input, compare: OUT1 output

P2.3/TA1/A3/VREF-/ VeREF- F3 29 27 I/O ADC10, analog input A3

Negative reference voltage input

General-purpose digital I/O pin

Timer_A, compare: OUT2 output

P2.4/TA2/A4/VREF+/ VeREF+ G3 30 28 I/O ADC10, analog input A4

Positive reference voltage output or input

General-purpose digital I/O pin

P2.5/ROSC C2 3 40 I/O Input for external DCO resistor to define DCO frequency

Input terminal of crystal oscillator

XIN/P2.6 A2 6 3 I/O General-purpose digital I/O pin

(1) TDO or TDI is selected via JTAG instruction.

MSP430F22x2

MSP430F22x4

www.ti.com

SLAS504G –JULY 2006–REVISED AUGUST 2012

Table 3. Terminal Functions, MSP430F22x2 (continued)

TERMINAL

NO. I/O DESCRIPTION

NAME YFF DA RHA

Output terminal of crystal oscillator

XOUT/P2.7 A1 5 2 I/O General-purpose digital I/O pin(2)

General-purpose digital I/O pin

USCI_B0 slave transmit enable

P3.0/UCB0STE/UCA0CLK/ B5 11 9 I/O

A5 USCI_A0 clock input/output

ADC10, analog input A5

General-purpose digital I/O pin

P3.1/UCB0SIMO/ A6 12 10 I/O USCI_B0 SPI mode: slave in/master out

UCB0SDA USCI_B0 I2C mode: SDA I2C data

General-purpose digital I/O pin

P3.2/UCB0SOMI/UCB0SCL A7 13 11 I/O USCI_B0 SPI mode: slave out/master in

USCI_B0 I2C mode: SCL I2C clock

General-purpose digital I/O pin

P3.3/UCB0CLK/UCA0STE B6 14 12 I/O USCI_B0 clock input/output

USCI_A0 slave transmit enable

General-purpose digital I/O pin

P3.4/UCA0TXD/ G6 25 23 I/O USCI_A0 UART mode: transmit data output

UCA0SIMO USCI_A0 SPI mode: slave in/master out

General-purpose digital I/O pin

P3.5/UCA0RXD/ G5 26 24 I/O USCI_A0 UART mode: receive data input

UCA0SOMI USCI_A0 SPI mode: slave out/master in

General-purpose digital I/O pin

P3.6/A6 F4 27 25 I/O ADC10 analog input A6

General-purpose digital I/O pin

P3.7/A7 G4 28 26 I/O ADC10 analog input A7

General-purpose digital I/O pin

P4.0/TB0 D6 17 15 I/O Timer_B, capture: CCI0A input, compare: OUT0 output

General-purpose digital I/O pin

P4.1/TB1 D7 18 16 I/O Timer_B, capture: CCI1A input, compare: OUT1 output

General-purpose digital I/O pin

P4.2/TB2 E6 19 17 I/O Timer_B, capture: CCI2A input, compare: OUT2 output

General-purpose digital I/O pin

P4.3/TB0/A12 E7 20 18 I/O Timer_B, capture: CCI0B input, compare: OUT0 output

ADC10 analog input A12

General-purpose digital I/O pin

P4.4/TB1/A13 F7 21 19 I/O Timer_B, capture: CCI1B input, compare: OUT1 output

ADC10 analog input A13

General-purpose digital I/O pin

P4.5/TB2/A14 F6 22 20 I/O Timer_B, compare: OUT2 output

ADC10 analog input A14

General-purpose digital I/O pin

P4.6/TBOUTH/A15 G7 23 21 I/O Timer_B, switch all TB0 to TB3 outputs to high impedance

ADC10 analog input A15

(2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to

this pad after reset.

MSP430F22x2

MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

www.ti.com

Table 3. Terminal Functions, MSP430F22x2 (continued)

TERMINAL

NO. I/O DESCRIPTION

NAME YFF DA RHA

General-purpose digital I/O pin

P4.7/TBCLK F5 24 22 I/O Timer_B, clock signal TBCLK input

Reset or nonmaskable interrupt input

RST/NMI/SBWTDIO B3 7 5 I Spy-Bi-Wire test data input/output during programming and test

Selects test mode for JTAG pins on Port 1. The device protection fuse is

connected to TEST.

TEST/SBWTCK D1 1 37 I Spy-Bi-Wire test clock input during programming and test

C1,

D3,

DVCC 2 38, 39 Digital supply voltage

D4,

E4, E5

C6,

AVCC C7, 16 14 Analog supply voltage

A3,

B1,

DVSS B2, 4 1, 4 Digital ground reference

C3,

B7,

AVSS 15 13 Analog ground reference

QFN Pad NA NA Pad NA QFN package pad; connection to DVSS recommended.

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