Texas Instruments Errata MSP430FG6426 User manual

Errata

MSP430FG6426 Microcontroller

ABSTRACT

This document describes the known exceptions to the functional specifications (advisories).

Table of Contents

1 Functional Advisories............................................................................................................................................................ 2

2 Preprogrammed Software Advisories.................................................................................................................................. 2

3 Debug Only Advisories.......................................................................................................................................................... 2

4 Fixed by Compiler Advisories............................................................................................................................................... 3

5 Nomenclature, Package Symbolization, and Revision Identification................................................................................ 4

5.1 Device Nomenclature.........................................................................................................................................................4

5.2 Package Markings..............................................................................................................................................................4

5.3 Memory-Mapped Hardware Revision (TLV Structure)....................................................................................................... 5

6 Advisory Descriptions............................................................................................................................................................6

7 Revision History................................................................................................................................................................... 22

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MSP430FG6426 Microcontroller 1

1 Functional Advisories

Advisories that affect the device's operation, function, or parametrics.

✓ The check mark indicates that the issue is present in the specified revision.

Errata Number

Rev A

COMP10 ✓

CPU37 ✓

CPU47 ✓

CTSD1 ✓

DAC5 ✓

DMA4 ✓

DMA7 ✓

DMA10 ✓

LCDB5 ✓

LCDB6 ✓

PMM11 ✓

PMM12 ✓

PMM14 ✓

PMM15 ✓

PMM18 ✓

PMM20 ✓

PMM26 ✓

PORT15 ✓

PORT19 ✓

RTC16 ✓

TB25 ✓

UCS11 ✓

USCI26 ✓

USCI34 ✓

USCI35 ✓

USCI39 ✓

USCI40 ✓

2 Preprogrammed Software Advisories

Advisories that affect factory-programmed software.

✓ The check mark indicates that the issue is present in the specified revision.

Errata Number

Rev A

BSL14 ✓

3 Debug Only Advisories

Advisories that affect only debug operation.

✓ The check mark indicates that the issue is present in the specified revision.

Errata Number

Rev A

EEM16 ✓

Functional Advisories www.ti.com

2MSP430FG6426 Microcontroller SLAZ669P – MAY 2015 – REVISED AUGUST 2021

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Errata Number

Rev A

EEM17 ✓

EEM19 ✓

EEM23 ✓

4 Fixed by Compiler Advisories

Advisories that are resolved by compiler workaround. Refer to each advisory for the IDE and compiler versions

with a workaround.

✓ The check mark indicates that the issue is present in the specified revision.

Errata Number

Rev A

CPU21 ✓

CPU22 ✓

CPU40 ✓

Refer to the following MSP430 compiler documentation for more details about the CPU bugs workarounds.

TI MSP430 Compiler Tools (Code Composer Studio IDE)

•MSP430 Optimizing C/C++ Compiler: Check the --silicon_errata option

•MSP430 Assembly Language Tools

MSP430 GNU Compiler (MSP430-GCC)

•MSP430 GCC Options: Check -msilicon-errata= and -msilicon-errata-warn= options

•MSP430 GCC User's Guide

IAR Embedded Workbench

•IAR workarounds for msp430 hardware issues

www.ti.com Fixed by Compiler Advisories

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MSP430FG6426 Microcontroller 3

5 Nomenclature, Package Symbolization, and Revision Identification

The revision of the device can be identified by the revision letter on the Package Markings or by the HW_ID

located inside the TLV structure of the device.

5.1 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP

MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These

prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully

qualified production devices (MSP).

XMS – Experimental device that is not necessarily representative of the final device's electrical specifications

MSP – Fully qualified production device

Support tool naming prefixes:

X: Development-support product that has not yet completed Texas Instruments internal qualification testing.

null: Fully-qualified development-support product.

XMS devices and X development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated

fully. TI's standard warranty applies.

Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.

TI recommends that these devices not be used in any production system because their expected end-use failure

rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature

range, package type, and distribution format.

5.2 Package Markings

ZQW113 BGA (ZQW), 113 Pin

PZ100 LQFP (PZ) 100 Pin

Nomenclature, Package Symbolization, and Revision Identification www.ti.com

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ZCA113 NFBGA (ZCA), 113 Pin

5.3 Memory-Mapped Hardware Revision (TLV Structure)

Die Revision TLV Hardware Revision

Rev A 10h

Further guidance on how to locate the TLV structure and read out the HW_ID can be found in the device User's

Guide.

www.ti.com Nomenclature, Package Symbolization, and Revision Identification

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MSP430FG6426 Microcontroller 5

6 Advisory Descriptions

BSL14 BSL Module

Category Software in ROM

Function BSL request to unlock the JTAG

Description The feature in the BSL to keep the JTAG unlocked by setting the bit

BSL_REQ_JTAG_OPEN in the return value has been disabled in this device.

Workaround None

COMP10 COMP Module

Category Functional

Function Comparator port output toggles when entering or leaving LPM3/LPM4

Description The comparator port pin output (CECTL1.CEOUT) erroneously toggles when device

enters or leaves LPM3/LPM4 modes under the following conditions:

1) Comparator is disabled (CECTL1.CEON = 0)

AND

2) Output polarity is enabled (CECTL1.CEOUTPOL = 1)

AND

3) The port pin is configured to have CEOUT functionality.

For example, if the CEOUT pin is high when the device is in Active Mode, CEOUT pin

becomes low when the device enters LPM3/LPM4 modes.

Workaround When the comparator is disabled, ensure at least one of the following:

1) Output inversion is disabled (CECTL.CEOUTPOL = 0)

2) Change pin configuration from CEOUT to GPIO with output low.

CPU21 CPU Module

Category Compiler-Fixed

Function Using POPM instruction on Status register may result in device hang up

Description When an active interrupt service request is pending and the POPM instruction is used to

set the Status Register (SR) and initiate entry into a low power mode , the device may

hang up.

Workaround None. It is recommended not to use POPM instruction on the Status Register.

Refer to the table below for compiler-specific fix implementation information.

Advisory Descriptions www.ti.com

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CPU21 (continued) CPU Module

IDE/Compiler Version Number Notes

IAR Embedded Workbench Not affected

TI MSP430 Compiler Tools (Code

Composer Studio) v4.0.x or later

User is required to add the compiler

or assembler flag option below. --

silicon_errata=CPU21

MSP430 GNU Compiler (MSP430-

GCC) MSP430-GCC 4.9 build 167 or later

CPU22 CPU Module

Category Compiler-Fixed

Function Indirect addressing mode with the Program Counter as the source register may produce

unexpected results

Description When using the indirect addressing mode in an instruction with the Program Counter (PC)

as the source operand, the instruction that follows immediately does not get executed.

For example in the code below, the ADD instruction does not get executed.

mov @PC, R7

add #1h, R4

Workaround Refer to the table below for compiler-specific fix implementation information.

IDE/Compiler Version Number Notes

IAR Embedded Workbench Not affected

TI MSP430 Compiler Tools (Code

Composer Studio) v4.0.x or later

User is required to add the compiler

or assembler flag option below. --

silicon_errata=CPU22

MSP430 GNU Compiler (MSP430-

GCC) MSP430-GCC 4.9 build 167 or later

CPU37 CPU Module

Category Functional

Function Wrong program trace display in the debugger while using conditional jump instructions

Description The state storage window displays an incorrect sequence of instructions when:

1. Conditional jump instructions are used to form a software loop

AND

2. A false condition on the jump breaks out of the loop

In such cases the trace buffer incorrectly displays the first instruction of the loop as the

instruction that is executed immediately after exiting the loop.

Example:

www.ti.com Advisory Descriptions

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MSP430FG6426 Microcontroller 7

CPU37 (continued) CPU Module

Actual Code:

mov #4,R4

LABEL mov #1,R5

dec R4

jnz LABEL

mov #2,R6

nop

State Storage Window Displays:

LABEL mov #1,R5

dec R4

jnz LABEL

mov #1,R5

nop

Workaround None

Note: This erratum affects the trace buffer display only. It does not affect code execution in

debugger or free run mode

CPU40 CPU Module

Category Compiler-Fixed

Function PC is corrupted when executing jump/conditional jump instruction that is followed by

instruction with PC as destination register or a data section

Description If the value at the memory location immediately following a jump/conditional jump

instruction is 0X40h or 0X50h (where X = don't care), which could either be an instruction

opcode (for instructions like RRCM, RRAM, RLAM, RRUM) with PC as destination

RAM), then the PC value is auto-incremented by 2 after the jump instruction is executed;

therefore, branching to a wrong address location in code and leading to wrong program

execution.

For example, a conditional jump instruction followed by data section (0140h).

@0x8012 Loop DEC.W R6

@0x8014 DEC.W R7

@0x8016 JNZ Loop

@0x8018 Value1 DW 0140h

Workaround In assembly, insert a NOP between the jump/conditional jump instruction and program

code with instruction that contains PC as destination register or the data section.

Refer to the table below for compiler-specific fix implementation information.

IDE/Compiler Version Number Notes

IAR Embedded Workbench IAR EW430 v5.51 or later

For the command line version add

the following information Compiler:

--hw_workaround=CPU40

Assembler:-v1

Advisory Descriptions www.ti.com

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CPU40 (continued) CPU Module

IDE/Compiler Version Number Notes

TI MSP430 Compiler Tools (Code

Composer Studio) v4.0.x or later

User is required to add the compiler

or assembler flag option below. --

silicon_errata=CPU40

MSP430 GNU Compiler (MSP430-

GCC) Not affected

CPU47 CPU Module

Category Functional

Function An unexpected Vacant Memory Access Flag (VMAIFG) can be triggered

Description An unexpected Vacant Memory Access Flag (VMAIFG) can be triggered, if a PC-

modifying instruction (e.g. - ret, push, call, pop, jmp, br) is fetched from the last addresses

(last 4 or 8 byte) of a memory (e.g.- FLASH, RAM, FRAM) that is not contiguous to a

higher, valid section on the memory map.

In debug mode using breakpoints the last 8 bytes are affected.

In free running mode the last 4 bytes are affected.

Workaround Edit the linker command file to make the last 4 or 8 bytes of affected memory sections

unavailable, to avoid PC-modifying instructions on these locations.

Remaining instructions or data can still be stored on these locations.

CTSD1 CTSD Module

Category Functional

Function CTSD16OFFG bit erroneously set while CTSD16 module is inactive

Description The CTSD16CTL.CTSD16OFFG bit is erroneously set when the CTSD16 module

is disabled and not actively converting (CTSD16CCTLx.CTSD16SC = 0). This

CTSD16CTL.CTSD16OFFG bit can only be cleared once the CTSD16 module is enabled

and actively converting (CTSD16CCTLx.CTSD16SC = 1).

This errata effectively nullifies the ability to trigger NMI interrupts in response to oscillator

faults, unless CTSD16 is kept enabled.

Workaround 1) If CTSD16 is enabled, and the fault condition is ensured not to be present, then

CTSD16OFFG and OFIFG can function normally. The only way to keep CTSD16 enabled

indefinitely is by setting CTSD16SC.

2) While CTSD16 is not enabled, the OFIFG bit cannot be used. The other bits sourcing

into it besides CTSD16OFFG (that is, XT1LFOFFG, XT1HFOFFG, XT2OFFG, and

DCOFFG) can be polled or checked by software individually; but the ability to trigger

the NMI upon OFIFG becoming set is no longer possible.

DAC5 DAC Module

Category Functional

Function Switching events on alternative DAC output pins can change output level of active DAC

output pin.

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MSP430FG6426 Microcontroller 9

DAC5 (continued) DAC Module

Description When the DAC output has multiple pin output options, switching events on unused

alternate pin output options, such as GPIO output voltage level transitions and pulses or

input signals that pass GPIO high or low thresholds, dynamically affect the output voltage

level of the DAC output in use. This effect only lasts for a short period after the switching

event.

Workaround If the dynamic voltage level effect on the chosen DAC output cannot be tolerated, see the

workarounds below:

A. Avoid high to low or low to high transitions on the alternate DAC output pin when

selected DAC output pin is active. Keep alternate pin pulled high or low when DAC is in

use.

B. Do not use pin featuring alternative DAC output, and keep in an output low state.

DMA4 DMA Module

Category Functional

Function Corrupted write access to 20-bit DMA registers

Description When a 20-bit wide write to a DMA address register (DMAxSA or DMAxDA) is interrupted

by a DMA transfer, the register contents may be unpredictable.

Workaround 1. Design the application to guarantee that no DMA access interrupts 20-bit wide

accesses to the DMA address registers.

2. When accessing the DMA address registers, enable the Read Modify Write disable bit

(DMARMWDIS = 1) or temporarily disable all active DMA channels (DMAEN = 0).

3. Use word access for accessing the DMA address registers. Note that this limits the

values that can be written to the address registers to 16-bit values (lower 64K of Flash).

DMA7 DMA Module

Category Functional

Function DMA request may cause the loss of interrupts

Description If a DMA request starts executing during the time when a module register containing an

interrupt flags is accessed with a read-modify-write instruction, a newly arriving interrupt

from the same module can get lost. An interrupt flag set prior to DMA execution would not

be affected and remain set.

Workaround 1. Use a read of Interrupt Vector registers to clear interrupt flags and do not use read-

modify-write instruction.

2. Disable all DMA channels during read-modify-write instruction of specific module

registers containing interrupts flags while these interrupts are activated.

Advisory Descriptions www.ti.com

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