Texas Instruments TVP5154A User manual

Application Report

SLEA104–July 2010

TVP5154A VBI Quick Start

.....................................................................................................................................................

ABSTRACT

The TVP5154A video decoder has an internal vertical data processor (VDP) that can be used to slice

various VBI data services such as V-Chip, Teletext (WST, NABTS), closed captioning (CC), wide screen

signaling (WSS), copy generation management system (CGMS), video program system (VPS), electronic

program guide (EPG or Gemstar), program delivery control (PDC) and vertical interval time code (VITC).

This application report provides an introduction to the VBI data slicing capabilities of the TVP5154A and

focuses on configuring the TVP5154A for the more commonly used VBI data services.

Contents

1 Introduction .................................................................................................................. 2

2 VDP Configuration RAM ................................................................................................... 4

3 Line Mode Registers ........................................................................................................ 5

4 Sliced Data Retrieval ....................................................................................................... 7

5 Managing Data Retrieval ................................................................................................... 7

6 FIFO Access ................................................................................................................. 8

7 Ancillary Data ................................................................................................................ 9

8 Full-Field Mode ............................................................................................................ 10

9 VBI Raw Data Mode ...................................................................................................... 10

Appendix A Subset of the TVP5154A VDP I2C Registers ................................................................. 12

Appendix B Sample WinVCC CMD File for VBI Setup ..................................................................... 20

Appendix C Example TVP5154A C Code .................................................................................... 21

Appendix D VBI Raw Data I2C Registers .................................................................................... 22

List of Figures

1 The VDP Configuration RAM is Loaded Prior to Line Mode Register Setup ....................................... 3

2 Example Load of WSS/CGMS Configuration RAM..................................................................... 5

3 Line Mode Setup for WSS/CGMS ........................................................................................ 6

4 Example WSS/CGMS Data Retrieval .................................................................................... 7

5 Line 21 Closed Caption ITU-R BT.656 Digital Output Capture with YUV Samples Present Raw Data

Mode disabled ............................................................................................................. 11

6 Line 21 Closed Caption ITU-R BT.656 Digital Output Capture in Raw Data ModeUV (chroma) data are

replaced with Y (luma) data.............................................................................................. 11

List of Tables

1 Supported Data Services .................................................................................................. 2

2 Configuration RAM Recommended Settings............................................................................ 4

3 Line Mode Configuration Bits for Supported Modes.................................................................... 6

4 Dedicated VDP Data Registers ........................................................................................... 7

5 Ancillary Data Header ...................................................................................................... 9

6 525-Line Raw Data Setup to Include Line 21.......................................................................... 10

7 625-Line Raw Data Setup................................................................................................ 10

SLEA104–July 2010 TVP5154A VBI Quick Start

Introduction

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1 Introduction

The TVP5154A video decoder has an internal Vertical Data Processor (VDP) that can be used to slice

various VBI data services such as V-Chip, Teletext (WST, NABTS), Closed Captioning (CC), Wide Screen

Signaling (WSS), Copy Generation Management System (CGMS), Video Program System (VPS),

Electronic Program Guide (EPG or Gemstar), Program Delivery Control (PDC), and Vertical Interval Time

Code (VITC). These data services are typically transmitted during the vertical blanking interval of the video

frame. Table 1 provides a summary of the supported data services including the line numbers on which

they are typically transmitted.

Table 1. Supported Data Services

VBI System Standard Line Number Number of Bytes Specification

Teletext WST A SECAM 6-23 (field 1, 2) 38 ITU-R BT 653-3

Teletext WST B PAL 6-22 (field 1, 2) 43 ITU-R BT 653-3

Teletext NABTS C NTSC-M 10-21 (field 1, 2) 34 ITU-R BT 653-3

Teletext NABTS D NTSC-J 10-21 (field 1, 2) 35 ITU-R BT 653-3

Closed Caption PAL 22 (field 1, 2) 2 EIA-608-D

Closed Caption NTSC 21 (field 1, 2) 2 EIA-608-D

WSS/CGMS PAL 23 (field 1, 2) 14 bits ITU-R BT 1119-1

WSS/CGMS NTSC 20 (field 1, 2) 20 bits IEC 61880

VITC PAL 6-22 9 SMPTE 12M-1999

VITC NTSC 10-20 9 SMPTE 12M-1999

VPS (PDC) PAL 16 13 ETS 300 231

V-Chip NTSC 21 (field 2) 2 EIA-744-A

Gemstar 1x NTSC 2

Gemstar 2x NTSC 5 with frame byte

User Any Programmable Programmable

A host or backend receiver can retrieve the sliced data using one of three methods:

• I2C access of dedicated Closed Caption, WSS, CGMS, VPS, Gemstar, VITC, and V-Chip data

registers.

• I2C access of an internal 512-byte FIFO used primarily for high-bandwidth data services such as

full-field teletext.

• As ITU-R BT.656 ancillary data, inserted by the TVP5154A in the data stream during the horizontal

blanking interval.

Note: This document will focus primarily on the more commonly used dedicated I2C data registers.

Prior to accessing the VBI sliced data, the TVP5154A must be configured for the desired VBI data service.

This includes loading of the VDP Configuration RAM (C-RAM) and the Line Mode registers that are used

to enable various data services. Detailed descriptions of the VBI related I2C registers are shown in

Appendix A.

2TVP5154A VBI Quick Start SLEA104–July 2010

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Introduction

Figure 1. The VDP Configuration RAM is Loaded Prior to Line Mode Register Setup

SLEA104–July 2010 TVP5154A VBI Quick Start

VDP Configuration RAM

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2 VDP Configuration RAM

The first step in configuring the TVP5154A for VBI data slicing is to load the VDP Configuration RAM

(C-RAM). The C-RAM defines the data slicing modes for the various data services, with each mode

having its own unique RAM address and 16 byte block of memory. Table 2 shows the recommended

setup values for the various data services that are supported. Prior to loading the C-RAM, the Line Mode

registers must all be programmed with a value of FFh to avoid conflict between the VDP and

microprocessor during the load process. Full field mode must also be disabled in I2C register CFh.

Table 2. Configuration RAM Recommended Settings

Index Address 0 1 2 3 4 5 6 7 8 9 A B C D E F

Reserved 000h Reserved

WST SECAM 010h AA AA FF FF E7 2E 20 A6 E4 B4 OE 0 7 0 10 0

Reserved 020h Reserved

WST PAL B 030h AA AA FF FF 27 2E 20 AB A4 72 10 0 7 0 10 0

Reserved 040h Reserved

WST PAL C 050h AA AA FF FF E7 2E 20 22 A4 98 0D 0 0 0 10 0

Reserved 060h Reserved

WST NTSC 070h AA AA FF FF 27 2E 20 23 63 93 0D 0 0 0 10 0

Reserved 080h Reserved

NABTS, NTSC 090h AA AA FF FF E7 2E 20 A2 63 93 0D 0 7 0 15 0

Reserved 0A0h Reserved

NABTS, NTSC-J 0B0h AA AA FF FF A7 2E 20 A3 63 93 0D 0 7 0 10 0

Reserved 0C0h Reserved

CC, PAL/SECAM 0D0h AA 2A FF 3F 04 51 6E 02 A4 7B 09 0 0 0 27 0

Reserved 0E0h Reserved

CC, NTSC 0F0h AA 2A FF 3F 04 51 6E 02 63 8C 09 0 0 0 27 0

Reserved 100h Reserved

WSS/CGMS, PAL/SECAM 110h 5B 55 C5 FF 0 71 6E 42 A4 CD 0F 0 0 0 3A 0

Reserved 120h Reserved

WSS/CGMS, NTSC 130h 38 0 3F 0 0 71 6E 43 63 7C 08 0 0 0 39 0

Reserved 140h Reserved

VITC, PAL/SECAM 150h 0 0 0 0 0 8F 6D 49 A4 85 08 0 0 0 4C 0

Reserved 160h Reserved

VITC, NTSC 170h 0 0 0 0 0 8F 6D 49 63 94 08 0 0 0 4C 0

Reserved 180h Reserved

VPS, PAL 190h AA AA FF FF BA CE 2B 8D A4 DA 0B 0 7 0 60 0

Reserved 1A0h Programmable

Gemstar Custom 1 1B0h 99 99 FF FF 05 51 6E 05 63 18 13 80 0 0 60 0

The C-RAM is accessed through the use of three I2C registers (C3h-C5h). Registers C4h and C5h must

be programmed with the 9-bit starting address of the block of C-RAM to be programmed. I2C read and

write operations are then performed indirectly using register C3h. The C-RAM address is automatically

incremented following each I2C transaction. Only the portion of the C-RAM that includes the data service

to be used needs to be programmed. If WSS/CGMS for NTSC is the only desired data service, for

example, only the 16 bytes starting at C-RAM address 130h need to be programmed. Figure 2 shows

example C code for loading the WSS/CGMS C-RAM.

4TVP5154A VBI Quick Start SLEA104–July 2010

// TVP5154A NTSC WSS/CGMS C-RAM Load Example

#define TVP5154A 0xB8; // TVP5154A main I2C address

byte I2C_Data;

int CRAM_Address, count;

byte I2CData ={0x14,0x02};

// recommended WSS/CGMS settings

byte WSS_ARRAY[]={0x38,0,0x3F,0,0,0x71,0x6E,0x43,0x63,0x7C,0x08,0,0,0,0x39,0};

I2C_RegAddress = 0xD0; // starting address of Line Mode registers

I2C_Data = 0xFF;

For (count = 0; count < 44; count ++)

{

I2CWriteByte(TVP5154A, I2C_RegAddress, I2C_Data); //write FFh to Line Mode registers

I2C_RegAddress ++;

}

I2CWriteByte(TVP5154A, 0xCF, 0); // disable full field mode

CRAM_Address = 0x130; // address of NTSC WSS/CGMS C-RAM block

I2CWriteByte(TVP5154A, 0xC4, 0x30); // load C4h with C-RAM address[7:0]

I2CWriteByte(TVP5154A, 0xC5, 0x01); // load C5h with C-RAM address[8]

For (count = 0; count < 16; count++)

{

I2CWriteByte(TVP5154A, 0xC3, WSS_ARRAY[count]); // write 16 bytes of WSS/CGMS C-RAM

} // data to register C3h.

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Line Mode Registers

Configuration RAM I2C Access Registers

Address C3h-C5h

Address 7 6 5 4 3 2 1 0

C3h Configuration data

C4h RAM address [7:0]

C5h Reserved RAM

address 8

Example: (Write 2 data bytes starting at C-RAM address 130h).

1. Set C-RAM starting address.

(a) Write 30h to register C4h (C-RAM address [7:0]).

(b) Write 01h to register C5h (C-RAM address [8]).

2. Write the two bytes (38h and 00h)

(a) Write 38h to register C3h. Write first byte to C-RAM address 130h.

(b) Write 00h to register C3h. Write next byte to C-RAM address 131h.

Figure 2. Example Load of WSS/CGMS Configuration RAM

3 Line Mode Registers

After the VDP Configuration RAM is loaded, the Line Mode Registers (D0h-FBh) must be properly

configured for the desired VBI data service. Each register in this register bank is linked to a specific video

line number and video field. Video lines 6 through 27 of both Field 1 and Field 2 are supported. For each

desired data service, the proper mode configuration bits need to be loaded into the line mode register that

is linked to the correct video line number. Additional data slicing options such as filtering, error correction,

and FIFO routing are also available in the line mode registers. Unused line mode and line address

registers must be programmed with FFh. A detailed description of these registers is shown in Appendix A.

The TVP5154A VDP is based on an NTSC line numbering convention, resulting in a 3-line VDP offset

SLEA104–July 2010 TVP5154A VBI Quick Start

// Example C Code for setting up WSS/CGMS Line Mode Registers

// Load C-RAM

// NTSC WSS/CGMS Line Mode setup for line 20 of both fields

I2CWriteByte(TVP5154A, 0xEC, 0x09); // line 20 field 1 (0xEC), mode bits = 0x09

I2CWriteByte(TVP5154A, 0xED, 0x09); // line 20 field 2 (0xED), mode bits = 0x09

I2CWriteByte(TVP5154A, 0xCB, 0x4E); // Set Pixel Alignment [7:0]to 0x4E

I2CWriteByte(TVP5154A, 0xCC, 0x00); // Set Pixel Alignment [9:8]to 0x00

// PAL WSS/CGMS Line Mode setup for line 23 (source input) of both fields.

// PAL line numbering has 3 line offset so the Line 26 line mode registers are used.

I2CWriteByte(TVP5154A, 0xF8, 0x08); // line 26 field 1 (0xF8), mode bits = 0x08

I2CWriteByte(TVP5154A, 0xF9, 0x08); // line 26 field 2 (0xF9), mode bits = 0x08

I2CWriteByte(TVP5154A, 0xCB, 0x4E); // Set Pixel Alignment [7:0]to 0x4E

I2CWriteByte(TVP5154A, 0xCC, 0x00); // Set Pixel Alignment [9:8]to 0x00

Line Mode Registers

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relative to actual PAL line numbers. For PAL systems, the Line Mode register for line “N+3” must be used

to configure a data service transmitted on line N of the input source. Figure 3 shows example C code for

configuring WSS/CGMS data services for NTSC and PAL. Included in this example is an I2C write to the

Pixel Alignment Registers (CBh-CCh), which define the horizontal position where data slicing begins. The

value used (4Eh) is recommended for all data services.

Table 3. Line Mode Configuration Bits for Supported Modes

Line Mode Register Name Video Line Number Description

(D0h-FCh) Bits [3:0]

0000b WST SECAM 6-23 (field 1, 2) Teletext, SECAM

0001b WST PAL B 6-22 (field 1, 2) Teletext, PAL, System B

0010b WST PAL C 6-22 (field 1, 2) Teletext, PAL, System C

0011b WST, NTSC B 10-21 (field 1, 2) Teletext, NTSC, System B

0100b NABTS, NTSC C 10-21 (field 1, 2) Teletext, NTSC, System C

0101b NABTS, NTSC D 10-21 (field 1, 2) Teletext, NTSC, System D (Japan)

0110b CC, PAL/SECAM 22 (field 1, 2) Closed caption PAL/SECAM

0111b CC, NTSC 21 (field 1, 2) Closed caption NTSC

1000b WSS/CGMS, PAL/SECAM 23 (field 1, 2) Wide-screen signal, PAL/SECAM

1001b WSS/CGMS, NTSC 20 (field 1, 2) Wide-screen signal, NTSC

1010b VITC, PAL/SECAM 6-22 Vertical interval timecode, PAL/SECAM

1011b VITC, NTSC 10-20 Vertical interval timecode, NTSC

1100b VPS, PAL 16 Video program system, PAL

1101b EPG/Gemstar Electronic program guide - Custom mode

1110b x x Reserved

1111b Active Video Active Video Active video/full field

Figure 3. Line Mode Setup for WSS/CGMS

6TVP5154A VBI Quick Start SLEA104–July 2010

// Example C Code for WSS/CGMS NTSC Sliced Data Read

// Load C-RAM

// Configure Line Mode Registers

byte Status;

byte WSSData[3];

I2CReadBuffer(TVP5154A,0xC6,&Status,1); //read 1 byte(status)from register C6h

if ((Status & 0x20) == 1)

{

I2CReadBuffer(TVP5154A,0x94,&WSSData[0],3); // if WSS/CGMS bit set,

// read the 3 WSS/CGMS bytes

// at WSS/CGMS data registers 94h–96h.

I2CWriteByte(TVP5154A,0xC6,0x20); // clear WSS/CGMS available status bit

}

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Sliced Data Retrieval

4 Sliced Data Retrieval

The TVP5154A provides dedicated I2C registers (see Table 4) for the retrieval of sliced data. Due to

higher bandwidth requirements, teletext data is stored in a 512-byte FIFO. With all other data services,

sliced data can be automatically sent to the dedicated registers or to the FIFO depending on the line mode

setup. The WSS/CGMS example in Figure 3 results in WSS/CGMS data being routed to the dedicated

WSS/CGMS data registers.

Table 4. Dedicated VDP Data Registers

VDP Closed Caption Data (field 1) 90h - 91h

VDP Closed Caption Data (field 2) 92h - 93h

VDP WSS/CGMS Data (field 1) 94h - 96h

VDP WSS/CGMS Data (field 2) 97h - 99h

VDP VPS (PAL) /Gemstar 2x (NTSC) 9Ah - A6h

Data

VDP VITC Data A7h - AFh

The internal 512-byte FIFO is used primarily for high-bandwidth teletext acquisition but can also be used

for capture of the other data services if enable in the Line Mode register. A header containing information

about the sliced data precedes all sliced data that is routed to the FIFO. The FIFO can be directly

accessed by the host at I2C address B0h. Bit 0 of the FIFO output control register (CDh) must be set to a

logic1 to enable host access to the FIFO.

5 Managing Data Retrieval

The VDP Status Registers (C6h) can be used to determine if sliced data is available. Unmasked data

available bits for the supported data services are available in this register.

VDP Status Register

Address C6h

76543210

FIFO full error FIFO empty TTX available CC field 1 CC field 2 WSS/CGMS VPS/Gemstar VITC available

available available available 2x available

A logic 1 indicates that sliced data is available. Once set, these bits need to be cleared after data retrieval. Writing a 1 to the appropriate

bit(s) in this register clears the status bit. Figure 4 shows an example WSS/CGMS data retrieval.

Figure 4. Example WSS/CGMS Data Retrieval

SLEA104–July 2010 TVP5154A VBI Quick Start

FIFO Access

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6 FIFO Access

The internal 512-byte FIFO is used primarily for high-bandwidth teletext acquisition but can also be used

for capture of the other data services. The FIFO can be directly accessed by the host at I2C address B0h.

Bit 0 of the VDP FIFO output control register (CDh) must be set to logic 1 to enable host access to the

FIFO. A header containing information about the sliced data precedes all sliced data that is routed to the

FIFO. A VDP FIFO Interrupt threshold register (C8h), FIFO word count register (C7h), and FIFO full/empty

status bits (C6h) are available for managing FIFO data flow.

8TVP5154A VBI Quick Start SLEA104–July 2010

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Ancillary Data

7 Ancillary Data

An option is available to enable transmission of sliced VBI data as ancillary data in the ITU-R BT.656

video data stream. In this mode, the sliced data is inserted on the Y[7:0] output terminals during the

horizontal blanking interval. An 8-byte header containing information about the sliced data is also inserted

in the data stream prior to the sliced data. The header includes a 00h, FFh, FFh preamble that identifies

the data as VBI ancillary data, so the host or backend must be able to distinguish between this preamble

and the ITU-R BT.656 embedded sync codes (FFh, 00h, 00h, E/SAV). The first header byte is inserted

immediately following the EAV code during the horizontal blanking interval of the digital line where it

occurred. The ancillary data header is summarized in Table 5.

The ancillary data mode is enabled by setting bit 6 in the appropriate line-mode register to a logic 1 and

the host-access enable bit (bit 0) in register CDh to a logic 0. When the ancillary data mode is enabled in

Table 5. Ancillary Data Header

Byte No. D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB) Description

0 0 0 0 0 0 0 0 0 Ancillary data preamble

111111111

211111111

3 NEP EP 0 1 0 DID2 DID1 DID0 Data ID (DID)

4 NEP EP F5 F4 F3 F2 F1 F0 Secondary data ID (SDID)

5 NEP EP N5 N4 N3 N2 N1 N0 Number of 32 bit data (NN)

6 Video line # [7:0] Internal Data ID0 (IDID0)

7 0 0 0 Data error Match #1 Match #2 Video line # [9:8] Internal Data ID1 (IDID1)

8 1. Data Data byte 1st word

9 2. Data Data byte

10 3. Data Data byte

11 4. Data Data byte

... ... ...

m-1. Data Data byte Nth word

m. data Data byte

CS [7:0] Checksum

4N+7 0 0 0 0 0 0 0 0 Fill byte

EP: Even parity for D0-D5

NEP: Negate even parity

DID: 91h: Sliced data from the vertical blanking interval of first field

53h: Sliced data from outside of the vertical blanking interval of first field

55h: Sliced data from the vertical blanking interval of second field

97h: Sliced data from outside of the vertical blanking interval of second field

SDID: This field holds the data format taken from the line-mode register of the corresponding line.

NN: Number of Dwords beginning with byte 8 through 4N+7. Note that each Dword is 4 bytes.

IDID0: Transaction video line number [7:0]

IDID1: Bit Transaction video line number [9:8].

0/1:

Bit 2: Match 2 flag.

Bit 3: Match 1 flag.

Bit 4: Value = 1 if a single error was detected in the EDC block. Value = 0 if no error was detected.

CS: Sum of D0-D7 of 1.Data through last data byte.

Fill byte: Fill byte makes a multiple of 4 bytes from byte zero to last fill byte.

Note: The number of bytes (m) varies depending on the VBI data service.

SLEA104–July 2010 TVP5154A VBI Quick Start

Full-Field Mode

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8 Full-Field Mode

Some teletext services transmit data on multiple video lines occurring anywhere in the video field. The

TVP5154A provides a full-field mode which arms VDP slicing for all lines in the video field. When full-field

mode is enabled, all video lines excluding those defined in the line-mode registers are sliced as specified

in the VDP full-field mode register (FCh). The full-field mode register uses the same mode configuration

format as the line-mode registers. Full-field mode is enabled by setting the full-field enable bit in register

CFh to a logic 1. Sliced data is then retrieved by I2C FIFO access or as ancillary data in the ITU-R BT.656

data stream.

9 VBI Raw Data Mode

The TVP5154A offers a VBI raw data mode for use in systems where VBI data slicing and processing is

handled in the digital backend receiver instead of the video decoder. In this mode of operation, the

decoders are configured to output raw 2x over-sampled luma data on the ITU-R BT.656 output during the

defined VBLK (vertical blanking) interval. The raw, un-sliced A/D video data is transmitted during the

active video portion of the line with chroma samples being replaced with the luma samples.

The default VBLK interval for Field 1 is defined as lines 1 through 20 for 525-line video formats and lines

623 through 23 for 625-line video formats. This interval may be adjusted to include additional lines.

Support for NTSC line 21 closed caption data, for example, requires extension of the VBLK interval to

include line 21.

The default VBLK interval for the TVP5154A is defined as lines 1 through 20 for 525-line video formats

and lines 623 through 23 for 625-line formats. The TVP5154A VBLK interval can be adjusted with the

VBLK Start and Stop registers (18h-19h). The TVP5154A VBLK Start and Stop registers provide relative

adjustments to the default VBLK interval. After configuring the desire VBLK interval, the Luma bypass (bit

4) in the Luminance Processing Control #1 register (07h) must be set to a logic 1 to enable raw data

output. Table 6 shows the default I2C registers with a modified VBLK interval for Line 21 inclusion, while

Table 7 shows the default 625-line setup. Also shown in Figure 5 and Figure 6 are digital captures of the

TVP5154A ITU-R BT.656 output for comparison of normal operation and raw data operation. Insertion of a

4-byte preamble (00h FFh FFh 60h) prior to the start of the raw data is optional in I2C register 07h.

Table 6. 525-Line Raw Data Setup to Include Line 21

I2C Subaddress Default I2C Data Description

07h 00h 10h Enable raw data (Luma bypass) and Preamble

18h 00h 00h VBLK Start = default line 1

19h 00h 01h VBLK Stop = default +1 to include line 21

Table 7. 625-Line Raw Data Setup

I2C Subaddress Default I2C Data Description

07h 00h 10h Enable raw data (Luma bypass) and Preamble

18h 00h 00h VBLK Start = default line 623

19h 00h 00h VBLK Stop = default

Note: Detailed descriptions of the TVP5154A I2C registers related to VBI Raw Data Mode are shown in

Appendix A.

Example (set up NTSC for raw data on lines 1 through 21)

1. Set up VBLK interval.

• Write 01h to register 19h to include line 21.

2. Enable Raw Data Mode

• Write 10h to register 07h to enable raw data mode.

10 TVP5154A VBI Quick Start SLEA104–July 2010

Table of contents

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