Texas Instruments DS90UH927Q User manual

DS90UH927Q

5MHz - 85MHz 24-bit Color FPD-Link III Serializer with HDCP

General Description

The DS90UH927Q serializer, in conjunction with a

DS90UH928Q or DS90UH926Q deserializer, provides a so-

lution for secure distribution of content-protected digital video

within automotive entertainment systems. This chipset trans-

lates a FPD-Link video interface into a single-pair high-speed

serialized interface. The digital video data is protected using

the industry standard High-Bandwidth Digital Content Protec-

tion (HDCP) copy protection scheme. The FPD-Link III serial

bus scheme supports full duplex, high speed forward channel

data transmission and low-speed back channel communica-

tion over a single differential link. Consolidation of audio,

video, and control data over a single differential pair reduces

the interconnect size and weight, while also eliminating skew

issues and simplifying system design.

The DS90UH927Q serializer embeds the clock, content pro-

tects the data payload, and level shifts the signals to high-

speed differential signaling. Up to 24 RGB data bits are

serialized along with three video control signals, and up to four

I2S data inputs.

The FPD-Link data interface allows for easy interfacing with

data sources while also minimizing EMI and bus width. EMI

on the high-speed FPD-Link III bus is minimized using low

voltage differential signaling, data scrambling and random-

ization, and dc-balancing.

The HDCP cipher engine is implemented in both the serializer

and deserializer. HDCP keys are stored in on-chip memory.

Features

●Integrated HDCP cipher engine with on-chip key storage

●Bidirectional control channel interface with I2C compatible

serial control bus

●Low EMI FPD-Link video input

●Supports high definition (720p) digital video format

●5MHz – 85MHz PCLK supported

●RGB888 + VS, HS, DE and I2S audio supported

●Up to 4 I2S Digital Audio inputs for surround sound

applications

●4 Bidirectional GPIO channels with 2 dedicated pins

●Single 3.3V supply with 1.8V or 3.3V compatible LVCMOS

I/O interface

●AC-coupled STP Interconnect up to 10 meters

●DC-balanced & scrambled Data with Embedded Clock

●Supports HDCP repeater application

●Internal pattern generation

●Low power modes minimize power dissipation

●Automotive grade product: AEC-Q100 Grade 2 qualified

●>8kV HBM and ISO 10605 ESD rating

●Backward compatible modes

Applications

●Automotive Display for Navigation

●Rear Seat Entertainment Systems

Applications Diagram

30193027

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

PRODUCTION DATA information is current as of

publication date. Products conform to specifications per

the terms of the Texas Instruments standard warranty.

Production processing does not necessarily include

testing of all parameters.

DS90UH927Q Pin Diagram

30193019

DS90UH927Q — Top View

Pin Descriptions

Pin Name Pin # I/O, Type Description

FPD-Link Input Interface

RxIN[3:0]+ 38, 34, 32, 30 I, LVDS True LVDS Data Inputs

Each pair requires external 100Ωdifferential termination for standard LVDS levels

RxIN[3:0]- 37, 33, 31, 29 I, LVDS Inverting LVDS Data Inputs

Each pair requires external 100Ωdifferential termination for standard LVDS levels

RxCLKIN+ 36 I, LVDS True LVDS Clock Input

The pair requires external 100Ωdifferential termination for standard LVDS levels

RxCLKIN- 35 I, LVDS Inverting LVDS Clock Input

The pair requires external 100Ωdifferential termination for standard LVDS levels

LVCMOS Parallel Interface

I2S_WC

I2S_CLK

I, LVCMOS

w/ pull down

Digital Audio Interface I2S Word Clock and I2S Bit Clock Inputs

Shared with GPIO_REG7 and GPIO_REG8

Table 3

I2S_DA

I2S_DB

I2S_DC

I2S_DD

I, LVCMOS

w/ pull down

Digital Audio Interface I2S Data Inputs

Shared with GPIO_REG6, GPIO_REG5, GPIO2, GPIO3

DS90UH927Q

Pin Name Pin # I/O, Type Description

GPIO[1:0] 40, 39 I/O,

LVCMOS

w/ pull down

General Purpose I/O

See Table 1

REPEAT 21 I, LVCMOS

w/ pull down

Repeater Mode Select

REPEAT = 0, Repeater Mode disabled (Default)

REPEAT = 1, Repeater Mode enabled

Requires a 10kΩpull-up if set HIGH

BKWD 22 I, LVCMOS

w/ pull down

Backward Compatible Mode Select

BKWD = 0, interfacing to DS90UH926/8Q (Default)

BKWD = 1, interfacing to DS90UR906/8Q, DS90UR916Q

Requires a 10kΩpull-up if set HIGH

MAPSEL 23 I, LVCMOS

w/ pull down

FPD-Link Input Map Select

MAPSEL = 0, LSBs on RxIN3± (Default)

MAPSEL = 1, MSBs on RxIN3±

See Figure 12and Figure 13

Requires a 10kΩpull-up if set HIGH

LFMODE 25 I, LVCMOS

w/ pull down

Low Frequency Mode Select

LFMODE = 0, 15MHz ≤RxCLKIN ≤85MHz (Default)

LFMODE = 1, 5MHz ≤RxCLKIN < 15MHz

Requires a 10kΩpull-up if set HIGH

Optional Parallel Interface

GPIO[3:2] 6, 5 I/O,

LVCMOS

w/ pull down

General Purpose I/O

Shared with I2S_DD and I2S_DC

See Table 1

GPIO_REG

[8:5]

2, 1, 3, 4 I/O,

LVCMOS

w/ pull down

Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB

See Table 2

Control and Configuration

PDB 18 I, LVCMOS

w/ pull-down

Power-down Mode Input Pin

Must be driven or pulled up to VDD33. Refer to “Power Up Requirements and PDB Pin" in

the Applications Information Section.

PDB = H, device is enabled (normal operation)

PDB = L, device is powered down.

When the device is in the powered down state, the Driver Outputs are both HIGH, the PLL

is shutdown, and IDD is minimized. Control Registers are RESET.

SCL 9 I/O,

LVCMOS

Open Drain

I2C Clock Input / Output Interface

Must have an external pull-up to VDD33. DO NOT FLOAT.

Recommended pull-up: 4.7kΩ.

SDA 10 I/O,

LVCMOS

Open Drain

I2C Data Input / Output Interface

Must have an external pull-up to VDD33.DO NOT FLOAT.

Recommended pull-up: 4.7kΩ.

IDx 11 I, Analog I2C Address Select

External pull-up to VDD33 is required under all conditions. DO NOT FLOAT.

Connect to external pull-up to VDD33 and pull-down to GND to create a voltage divider.

See Figure 23and Table 4

Status

INTB 27 O, LVCMOS

Open Drain

HDCP Interrupt

INTB = H, normal

INTB = L, Interrupt request

Recommended pull-up: 4.7kΩto VDDIO. DO NOT FLOAT.

FPD-Link III Serial Interface

DOUT+ 17 I/O, LVDS True Output

The output must be AC-coupled with a 0.1µF capacitor.

DS90UH927Q

Pin Name Pin # I/O, Type Description

DOUT- 16 I/O, LVDS Inverting Output

The output must be AC-coupled with a 0.1µF capacitor.

CMF 20 Analog Common Mode Filter.

Connect 0.1µF to GND (required)

Power* and Ground

VDD33_A

VDD33_B

Power Power to on-chip regulator 3.0 V - 3.6 V. Each pin requires a 4.7µF capacitor to GND

VDDIO 7, 24 Power LVCMOS I/O Power 1.8 V ±5% OR 3.0 V - 3.6 V. Each pin requires 4.7µF capacitor to

GND

GND DAP Ground Large metal contact at the bottom center of the device package Connect to the ground

plane (GND) with at least 9 vias.

Regulator Capacitor

CAPP12

CAPHS12

CAPLVD12

CAP Decoupling capacitor connection for on-chip regulator

Each requires a 4.7µF decoupling capacitor to GND.

CAPL12 8 CAP Decoupling capacitor connection for on-chip regulator

Requires two 4.7µF decoupling capacitors to GND

Other

RES[1:0] 15, 13 GND Reserved

Connect to GND.

* The VDD (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.

DS90UH927Q

Block Diagram

30193028

Ordering Information

NSID Package Description Quantity SPEC Package ID

DS90UH927QSQE 40-pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch 250 NOPB SQA40A

DS90UH927QSQ 40-pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch 1000 NOPB SQA40A

DS90UH927QSQX 40-pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch 2000 NOPB SQA40A

Note: Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market,

including defect detection methodologies. Reliability qualification is compliant with the requirements and temperature grades

defined in the AEC Q100 standard. Automotive Grade products are identified with the letter Q. For more information go to

http://www.ti.com/automotive.

DS90UH927Q

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for

availability and specifications.

Parameter DS90UH927Q Unit

Supply Voltage – VDD33 −0.3 to +4.0 V

Supply Voltage – VDDIO −0.3 to +4.0 V

LVCMOS I/O Voltage −0.3 to (VDDIO + 0.3) V

Serializer Output Voltage −0.3 to +2.75 V

Junction Temperature +150 °C

Storage Temperature −65 to +150 °C

40 LLP Package Maximum Power Dissipation Capacity at 25°C

Derate above 25°C 1/ θJA °C/W

θJA 28.0 °C/W

θJC 4.4 °C/W

ESD Rating (IEC, powered-up only), RD = 330Ω, CS= 150pF

Air Discharge

(DOUT+, DOUT−)≥±15 kV

Contact Discharge

(DOUT+, DOUT−)≥±8 kV

ESD Rating (ISO10605), RD = 330Ω, CS= 150pF

Air Discharge

(DOUT+, DOUT−)≥±15 kV

Contact Discharge

(DOUT+, DOUT−)≥±8 kV

ESD Rating (ISO10605), RD= 2kΩ, CS= 150pF or 330pF

Air Discharge

(DOUT+, DOUT−)≥±15 kV

Contact Discharge

(DOUT+, DOUT−)≥±8 kV

ESD Rating (HBM) ≥±8 kV

ESD Rating (CDM) ≥±1.25 kV

ESD Rating (MM) ≥±250 V

For soldering specifications:

see product folder at www.ti.com and www.ti.com/lit/an/snoa549c/snoa549c.pdf

Recommended Operating Conditions

Parameter Min Nom Max Units

Supply Voltage (VDD33) 3.0 3.3 3.6 V

LVCMOS Supply Voltage (VDDIO) Note: VDDIO < VDD33+0.3V 3.0 3.3 3.6 V

LVCMOS Supply Voltage (VDDIO) 1.71 1.8 1.89 V

Operating Free Air

Temperature (TA)−40 +25 +105 °C

PCLK Frequency 5 85 MHz

Supply Noise ((Note 5)) 100 mVP-P

DS90UH927Q

DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2, Note 3, Note 4)

Symbol Parameter Conditions Pin/Freq. Min Typ Max Units

LVCMOS I/O

VIH High Level Input Voltage VDDIO = 3.0V to 3.6V

(Note 14)

PDB

2.0 VDDIO V

VIL Low Level Input Voltage VDDIO = 3.0V to 3.6V

(Note 14)GND 0.8 V

IIN Input Current

VIN = 0V or VDDIO = 3.0V to

3.6V

(Note 14)

−15 ±1 +15 μA

VIH High Level Input Voltage

VDDIO = 3.0V to 3.6V

GPIO[1:0]

I2S_CLK

I2S_WC

I2S_D

[A,B,C,D]

LFMODE

MAPSEL

BKWD

REPEAT

2.0 VDDIO V

VDDIO = 1.71V to 1.89V 0.65*

VDDIO

VDDIO V

VIL Low Level Input Voltage

VDDIO = 3.0V to 3.6V GND 0.8 V

VDDIO = 1.71V to 1.89V GND 0.35*

VDDIO

IIN Input Current VIN = 0V or

VDDIO

VDDIO = 3.0V

to 3.6V −15 ±1 +15 μA

VDDIO =

1.71V to

1.89V

−15 ±1 +15 μA

VOH High Level Output Voltage IOH = −4mA

VDDIO = 3.0V

to 3.6V

GPIO[3:0],

GPO_REG

[8:5]

2.4 VDDIO V

VDDIO =

1.71V to

1.89V

VDDIO -

0.45 VDDIO V

VOL Low Level Output Voltage

IOL = +4mA VDDIO = 3.0V

to 3.6V GND 0.4 V

VDDIO =

1.71V to

1.89V

GND 0.45 V

IOS Output Short Circuit Current VOUT = 0V −55 mA

IOZ TRI-STATE® Output Current VOUT = 0V or VDDIO, PDB = L, −15 +15 μA

FPD-Link LVDS Receiver

VTH Threshold High Voltage

VCM = 1.2V

RxCLKIN±

RxIN[3:0]±

+100 mV

VTL Threshold Low Voltage −100 mV

|VID|Differential Input Voltage

Swing 200 600 mV

VCM Common Mode Voltage 0 1.2 2.4 V

IIN Input Current −10 +10 μA

DS90UH927Q

Symbol Parameter Conditions Pin/Freq. Min Typ Max Units

FPD-LINK III CML Driver

VODp-p

Differential Output Voltage

(DOUT+) – (DOUT-) RL = 100Ω

DOUT±

800 1000 1200 mVp-p

ΔVOD Output Voltage Unbalance 1 50 mV

VOS Offset Voltage – Single-ended RL = 100Ω

2.5-0.2

5*VODp-

p (TYP)

ΔVOS

Offset Voltage Unbalance

Single-ended 1 50 mV

IOS Output Short Circuit Current DOUT+/- = 0V, PDB = L or H mA

Internal Termination

Resistance - Differential 80 100 120 Ω

Supply Current

IDD1

Supply Current

RL = 100Ω,

PCLK = 85MHz

Checkerboard Pattern

VDD33= 3.6V 135 160 mA

IDDIO1

VDDIO = 3.6V 100 500 μA

VDDIO =

1.89V 200 600 μA

IDD2

Random Pattern

PRBS7

VDD33= 3.6V 133 mA

IDDIO2

VDDIO = 3.6V 100 μA

VDDIO =

1.89V 100 μA

IDDS

Supply Current — Remote

Auto Power Down

reg_0x01[7]=1, Back channel

Idle

VDD33 = 3.6V 1.2 2.4 mA

IDDIOS

VDDIO = 3.6V 4 30 μA

VDDIO =

1.89V 5 30 μA

IDDZ

Supply Current — Power Down PDB = 0V, All other LVCMOS

inputs = 0V

VDD33 = 3.6V 1 2.2 mA

IDDIOZ

VDDIO = 3.6V 8 20 μA

VDDIO =

1.89V 4 20 μA

DS90UH927Q

AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2, Note 3, Note 4)

Symbol Parameter Conditions Pin/Freq. Min Typ Max Units

FPD-Link LVDS INPUT

tRSP Receiver Strobe Position Figure 4 RxCLKIN±,

RXIN[3:0]±

0.25 0.5 0.75 UI

FPD-Link III CML I/O

tLHT CML Output Low-to-High

Transition Time Figure 3 DOUT+,

DOUT-

100 140 ps

tHLT CML Output High-to-Low

Transition Time 100 140 ps

tPLD

Serializer PLL Lock Time

Figure 5, (Note 6) PCLK =

5MHz to

85MHz

5 ms

tSD Delay — Latency Figure 6 146*T ns

tTJIT

Output Total Jitter,

Bit Error Rate ≤1E-9

Figure 7, (Note 12, Note 11,

Note 8, Note 7)

Checkerboard Pattern

PCLK = 5MHz

Figure 8 RxCLKIN±

0.17 0.2 UI

Checkerboard Pattern

PCLK = 85MHz

Figure 8

0.26 0.29 UI

tIJIT

Input Jitter Tolerance, Bit Error

Rate ≤1E-9

(Note 7, Note 10)

f/40 < Jitter Freq < f/20, DES

= DS90UH926Q RxCLKIN±, f

= 78MHz

0.6 UI

f/40 < Jitter Freq < f/20, DES

= DS90UH928Q 0.5 UI

I2S Receiver

TI2S I2S Clock Period

Figure 10, (Note 8, Note 16)

RxCLKIN± f=5MHz to 85MHz I2S_CLK,

PCLK =

5MHz to

85MHz

>4/

PCLK

or >77

THC I2S Clock High Time

Figure 10, (Note 16)

I2S_CLK 0.35 TI2S

TLC I2S Clock Low Time

Figure 10, (Note 16)

I2S_CLK 0.35 TI2S

tsr I2S Set-up Time I2S_WC

I2S_D

[A,B,C,D]

0.2 TI2S

thtr I2S Hold Time I2S_WC

I2S_D

[A,B,C,D]

0.2 TI2S

Other I/O

tGPIO,FC

GPIO Pulse Width, Forward

Channel

GPIO[3:0],

PCLK =

5MHz to

85MHz

>2/

PCLK s

tGPIO,BC GPIO Pulse Width, Back

Channel

GPIO[3:0] 20 µs

DS90UH927Q

Recommended Timing for the Serial Control Bus

Over 3.3V supply and temperature ranges unless otherwise specified. (Note 2, Note 3, Note 4)

Symbol Parameter Conditions Min Typ Max Units

fSCL SCL Clock Frequency Standard Mode 0 100 kHz

Fast Mode 0 400 kHz

tLOW SCL Low Period Standard Mode 4.7 µs

Fast Mode 1.3 µs

tHIGH SCL High Period Standard Mode 4.0 µs

Fast Mode 0.6 µs

tHD;STA Hold time for a start or a

repeated start condition

Figure 9

Standard Mode 4.0 µs

Fast Mode 0.6 µs

tSU:STA Set Up time for a start or a

repeated start condition

Figure 9

Standard Mode 4.7 µs

Fast Mode 0.6 µs

tHD;DAT Data Hold Time

Figure 9

Standard Mode 0 3.45 µs

Fast Mode 0 0.9 µs

tSU;DAT Data Set Up Time

Figure 9

Standard Mode 250 ns

Fast Mode 100 ns

tSU;STO Set Up Time for STOP

Condition

Figure 9

Standard Mode 4.0 µs

Fast Mode 0.6 µs

tBUF

Bus Free Time

Between STOP and START

Figure 9

Standard Mode 4.7 µs

Fast Mode 1.3 µs

SCL & SDA Rise Time,

Figure 9

Standard Mode 1000 ns

Fast Mode 300 ns

SCL & SDA Fall Time,

Figure 9

Standard Mode 300 ns

Fast mode 300 ns

DC and AC Serial Control Bus Characteristics

Over 3.3V supply and temperature ranges unless otherwise specified. (Note 2, Note 3, Note 4)

Symbol Parameter Conditions Min Typ Max Units

VIH Input High Level SDA and SCL 0.7*

VDDIO

VDD33 V

VIL Input Low Level Voltage SDA and SCL GND 0.3*

VDD33

VHY Input Hysteresis >50 mV

VOL SDA or SCL, IOL = 1.25mA 0 0.36 V

Iin SDA or SCL, Vin = VDDIO or GND -10 +10 µA

tRSDA RiseTime – READ SDA, RPU = 10kΩ, Cb ≤400pF, Figure 9 430 ns

tFSDA Fall Time – READ 20 ns

tSU;DAT Set Up Time — READ Figure 9 560 ns

tHD;DAT Hold Up Time — READ Figure 9 615 ns

tSP Input Filter 50 ns

Cin Input Capacitance SDA or SCL <5 pF

DS90UH927Q

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