ST STM32F10 Series Installation and operating instructions

November 2011 Doc ID 13675 Rev 7 1/28

AN2586

Application note

Getting started with STM32F10xxx hardware development

Introduction

This application note is intended for system designers who require a hardware

implementation overview of the development board features such as the power supply, the

clock management, the reset control, the boot mode settings and the debug management. It

shows how to use the low-density value line, low-density, medium-density value line,

medium-density, high-density, XL-density and connectivity line STM32F10xxx product

families and describes the minimum hardware resources required to develop an

STM32F10xxx application.

Detailed reference design schematics are also contained in this document with descriptions

of the main components, interfaces and modes.

Glossary

●Low-density value line devices are STM32F100xx microcontrollers where the Flash

memory density ranges between 16 and 32 Kbytes.

●Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx

microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.

●Medium-density value line devices are STM32F100xx microcontrollers where the

Flash memory density ranges between 64 and 128 Kbytes.

●Medium-density devices are STM32F100xx, STM32F101xx, STM32F102xx and

STM32F103xx microcontrollers where the Flash memory density ranges between 64

and 128 Kbytes.

●High-density value line devices are STM32F100xx microcontrollers where the Flash

memory density ranges between 256 and 512 Kbytes.

●High-density devices are STM32F101xx and STM32F103xx microcontrollers where

the Flash memory density ranges between 256 and 512 Kbytes.

●XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the

Flash memory density ranges between 768 Kbytes and 1 Mbyte.

●Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

www.st.com

Contents AN2586

2/28 Doc ID 13675 Rev 7

Contents

1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1.1 Independent A/D converter supply and reference voltage . . . . . . . . . . . . 6

1.1.2 Battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3 Reset and power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3.1 Power on reset (POR) / power down reset (PDR) . . . . . . . . . . . . . . . . . . 8

1.3.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.3.3 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1 HSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1.1 External source (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1.2 External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . 12

2.2 LSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2.1 External source (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2.2 External crystal/ceramic resonator (LSE crystal) . . . . . . . . . . . . . . . . . . 13

2.3 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1 Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2 Boot pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3 Embedded boot loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.3.3 Internal pull-up and pull-down resistors on JTAG pins . . . . . . . . . . . . . . 19

4.3.4 SWJ debug port connection with standard JTAG connector . . . . . . . . . 19

AN2586 Contents

Doc ID 13675 Rev 7 3/28

5 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1 Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.2 Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.3 Ground and power supply (VSS, VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.4 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.5 Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.6 Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.1.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.1.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.1.3 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.1.4 SWJ interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.1.5 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.2 Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

List of tables AN2586

4/28 Doc ID 13675 Rev 7

List of tables

Table 1. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 2. Debug port pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 3. SWJ I/O pin availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 4. Mandatory components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 5. Optional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 6. Reference connection for all packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 7. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

AN2586 List of figures

Doc ID 13675 Rev 7 5/28

List of figures

Figure 1. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. PVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 5. Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 6. External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 7. Crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 8. External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 9. Crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 10. Boot mode selection implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 11. Host-to-board connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 12. JTAG connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 13. Typical layout for VDD/VSS pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 14. STM32F103ZE(T6) microcontroller reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Power supplies AN2586

6/28 Doc ID 13675 Rev 7

1 Power supplies

1.1 Introduction

The device requires a 2.0 V to 3.6 V operating voltage supply (VDD). An embedded regulator

is used to supply the internal 1.8 V digital power.

The real-time clock (RTC) and backup registers can be powered from the VBAT voltage when

the main VDD supply is powered off.

Figure 1. Power supply overview

Note: VDDA and VSSA must be connected to VDD and VSS, respectively.

1.1.1 Independent A/D converter supply and reference voltage

To improve conversion accuracy, the ADC has an independent power supply that can be

filtered separately, and shielded from noise on the PCB.

●the ADC voltage supply input is available on a separate VDDA pin

●an isolated supply ground connection is provided on the VSSA pin

When available (depending on package), VREF– must be tied to VSSA.

On 100-pin and 144-pin packages

To ensure a better accuracy on low-voltage inputs, the user can connect a separate external

reference voltage ADC input on VREF+. The voltage on VREF+ may range from 2.4 V to

VDDA.

A/D converter

I/O Ring

BKP registers

Temp. sensor

Reset block

Standby circuitry

PLL

(Wakeup logic,

IWDG)

RTC

Voltage regulator

Core

memories'

digital

peripherals

Low voltage detector

SSA

) V

REF–

DDA

domain

domain 1.8 V domain

Backup domain

LSE crystal 32 KHz oscillator

RCC BDCR register

ai14863

(from 2.4 V up to V

DDA

) V

REF+

) V

DDA

) V

SSA

) V

BAT

AN2586 Power supplies

Doc ID 13675 Rev 7 7/28

On packages with 64 pins or less

The VREF+ and VREF- pins are not available, they are internally connected to the ADC

voltage supply (VDDA) and ground (VSSA).

1.1.2 Battery backup

To retain the content of the Backup registers when VDD is turned off, the VBAT pin can be

connected to an optional standby voltage supplied by a battery or another source.

The VBAT pin also powers the RTC unit, allowing the RTC to operate even when the main

digital supply (VDD) is turned off. The switch to the VBAT supply is controlled by the power

down reset (PDR) circuitry embedded in the Reset block.

If no external battery is used in the application, it is highly recommended to connect VBAT

externally to VDD.

1.1.3 Voltage regulator

The voltage regulator is always enabled after reset. It works in three different modes

depending on the application modes.

●in Run mode, the regulator supplies full power to the 1.8 V domain (core, memories and

digital peripherals)

●in Stop mode, the regulator supplies low power to the 1.8 V domain, preserving the

contents of the registers and SRAM

●in Standby mode, the regulator is powered off. The contents of the registers and SRAM

are lost except for those concerned with the Standby circuitry and the Backup domain.

1.2 Power supply schemes

The circuit is powered by a stabilized power supply, VDD.

●Caution:

– If the ADC is used, the VDD range is limited to 2.4 V to 3.6 V

– If the ADC is not used, the VDD range is 2.0 V to 3.6 V

●The VDD pins must be connected to VDD with external decoupling capacitors (one

100 nF Ceramic capacitor for each VDD pin + one Tantalum or Ceramic capacitor (min.

4.7 µF typ.10 µF).

●The VBAT pin can be connected to the external battery (1.8 V < VBAT < 3.6 V). If no

external battery is used, it is recommended to connect this pin to VDD with a 100 nF

external ceramic decoupling capacitor.

●The VDDA pin must be connected to two external decoupling capacitors (100 nF

Ceramic + 1 µF Tantalum or Ceramic).

●The VREF+ pin can be connected to the VDDA external power supply. If a separate,

external reference voltage is applied on VREF+, a 100 nF and a 1 µF capacitors must be

connected on this pin. In all cases, VREF+ must be kept between 2.4 V and VDDA.

●Additional precautions can be taken to filter analog noise:

–V

DDA can be connected to VDD through a ferrite bead.

–TheV

REF+ pin can be connected to VDDA through a resistor (typ. 47 Ω).

Power supplies AN2586

8/28 Doc ID 13675 Rev 7

Figure 2. Power supply scheme

1. Optional. If a separate, external reference voltage is connected on VREF+, the two capacitors (100 nF and

1 µF) must be connected.

2. VREF+ is either connected to VDDA or to VREF.

3. N is the number of VDD and VSS inputs.

1.3 Reset and power supply supervisor

1.3.1 Power on reset (POR) / power down reset (PDR)

The device has an integrated POR/PDR circuitry that allows proper operation starting from

2V.

The device remains in the Reset mode as long as VDD is below a specified threshold,

VPOR/PDR, without the need for an external reset circuit. For more details concerning the

power on/power down reset threshold, refer to the electrical characteristics in the low-

density, medium-density, high-density, XL-density, and connectivity line STM32F10xxx

datasheets.

Figure 3. Power on reset/power down reset waveform

VBAT

STM32F10xxx

N × 100 nF

VDD

+ 1 × 10 µF

100 nF + 1 µF

(note 1)

Battery

VBAT VREF+

VDDA

VSSA

VREF–

VDD 1/2/3/.../N

VSS 1/2/3/.../N

VREF

VDD

ai14865b

VDD

POR

PDR

40 mV

hysteresis

Temporization

tRSTTEMPO

RESET

ai14364

AN2586 Power supplies

Doc ID 13675 Rev 7 9/28

1.3.2 Programmable voltage detector (PVD)

You can use the PVD to monitor the VDD power supply by comparing it to a threshold

selected by the PLS[2:0] bits in the Power control register (PWR_CR).

The PVD is enabled by setting the PVDE bit.

A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate

whether VDD is higher or lower than the PVD threshold. This event is internally connected to

EXTI Line16 and can generate an interrupt if enabled through the EXTI registers. The PVD

output interrupt can be generated when VDD drops below the PVD threshold and/or when

VDD rises above the PVD threshold depending on the EXTI Line16 rising/falling edge

configuration. As an example the service routine can perform emergency shutdown tasks.

Figure 4. PVD thresholds

1.3.3 System reset

A system reset sets all registers to their reset values except for the reset flags in the clock

controller CSR register and the registers in the Backup domain (see Figure 1).

A system reset is generated when one of the following events occurs:

1. A low level on the NRST pin (external reset)

2. window watchdog end-of-count condition (WWDG reset)

3. Independent watchdog end-of-count condition (IWDG reset)

4. A software reset (SW reset)

5. Low-power management reset

The reset source can be identified by checking the reset flags in the Control/Status register,

RCC_CSR.

VDD

100 mV

hysteresis

PVD threshold

PVD output

ai14365

Power supplies AN2586

10/28 Doc ID 13675 Rev 7

The STM32F1xx does not require an external reset circuit to power-up correctly. Only a pull-

down capacitor is recommended to improve EMS performance by protecting the device

against parasitic resets. See Figure 5.

Charging and discharging a pull-down capacitor through an internal resistor increases the

device power consumption. The capacitor recommended value (100 nF) can be reduced to

10 nF to limit this power consumption;

Figure 5. Reset circuit

205

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77$'RESET

)7$'RESET

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GENERATOR 0OWERRESET

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