ST STM32C0 Series User manual
Introduction
This document is addressed to system designers who require an overview of the hardware implementation of development
board features (such as power supply, clock management, reset control, boot mode settings and debug management). It shows
how to use STM32C0 Series devices and describes the minimum hardware resources required to develop an application.
This document also includes detailed reference design schematics with the description of the main components, interfaces and
modes.
Getting started with STM32C0 Series hardware development
AN5673
Application note
AN5673 - Rev 2 - December 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
1Power supplies and reset sources
This section describes the power supply schemes and the reset and power supply supervisor on STM32C0
Series devices, based on an Arm® core.
Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
1.1 Power supplies
The STM32C0 series devices require a 2.0 to 3.6 V operating supply voltage (VDD). Several different power
supplies are provided to specific peripherals:
• VDD = 2.0 to 3.6 V
VDD is the external power supply for the internal regulator and the system analog such as reset, power
management and internal clocks. It is provided externally through the VDD pin.
Note that the power-on reset happens when the VPOR(max) = 1.94 V threshold is crossed by VDD and
that this value is below 2 V (VDD recommended minimum value). Once this threshold is crossed, the
functionality is guaranteed down to the power-down reset threshold VPDR(min) = 1.92 V.
• VDDA = 2.0 to 3.6 V
VDDA is the analog power supply for the A/D converter. Its voltage level is identical to the VDD voltage, as
it is provided externally through VDD pin (VDD and VDDA are shorted due to the low number of pins on the
packages proposed for the STM32C0 series).
• VDDIO = VDD
VDDIO is the power supply for the I/Os. Its voltage level is identical to VDD voltage as it is provided
externally through VDD pin (VDD and VDDIO are shorted due to the low number of pins on the packages
proposed for the STM32C0 series).
• VREF+ is the input reference voltage for the ADC. Its voltage level is identical to the VDD voltage as it is
provided externally through VDD pin (VDD and VDDIO are shorted due to the low number of pins on the
packages proposed for STM32C0 series). Package with separate VREF+ pin, VREF+ must be between 2 V
and VDDA or can be grounded when the ADC is not active. VREF- is bonded to VSS and VSSA, whatever the
package.
• VCORE
An embedded linear voltage regulator is used to supply the VCORE internal digital power, the power supply
for digital peripherals, SRAM, and flash memory. The flash memory is also supplied by VDD.
Table 1. Power supplies of STM32C0 series
Power supply STM32C0 series
VDD 2.0 to 3.6 V
VREF+ VREF+ must be between 2 V and VDDA(1)
1. This is only true for the packages where a dedicated VREF+ pin is present. In the other cases, VDD, VDDA and VREF+ are
shorted and correspond to the same voltage.
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Power supplies and reset sources
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Figure 1. STM32C0 series power supply
DT54392V2
VDD
RTC
Kernel logic
(CPU, digital and
memories)
Level shifter
IO
logic
IN
OUT
Regulator
GPIOs
1 x 100 nF
+ 1 x 4.7 µF
VDD/VDDA
VCORE
VDDIO
ADC
VREF+ (1)
VSS/VSSA
VREF
100 nF
VSS
VSSA
VDDA
VDD
VREF+
(1): Internally connected to the VDD/VDDA pin on packages without VREF+ pin.
Note: Power supply pin pairs (VDD/VDDA and VSS/VSSA) must be decoupled with filtering ceramic capacitors as
shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the
underside of the PCB to ensure the good functionality of the device.
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Power supplies
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1.2 Power supply supervisor
1.2.1 Power-on reset (POR) / power-down reset (PDR) / brown-out reset (BOR)
The devices feature an integrated power-on reset (POR) / power-down reset (PDR), coupled with a brown-out
reset (BOR) circuitry. The POR/PDR is active in all power modes.
The BOR can be enabled or disabled only through option bytes. It is not available in Shutdown mode.
When the BOR is enabled, four BOR levels can be selected through option bytes, with independent configuration
for rising and falling thresholds. During power-on, the BOR keeps the device under reset until the VDD supply
voltage reaches the specified BOR rising threshold (VBORRx). At this point, the device reset is released and the
system can start.
During power-down, when VDD drops below the selected BOR falling threshold (VBORFx), the device is put under
reset again.
Note: It is not allowed to configure BOR falling threshold (VBORFx) to a value higher than BOR rising threshold
(VBORRx).
Figure 2. POR, PDR, and BOR thresholds
VDD
VBORR4
VBORF4
VBORR3
VBORF3
VBORR2
VBORF2
VBORR1
VBORF1
VPOR
VPDR
t
tRSTTEMPO
tRSTTEMPO
Reset with BOR off
Reset with BOR on
(VBORR4 VBORF1)
POR/BOR rising thresholds
PDR/BOR falling thresholds
Note: The reset temporization tRSTTEMPO starts when VDD crosses VPOR threshold, indifferently from the configuration
of the BOR option bits.
For more details on the brown-out reset thresholds, refer to the electrical characteristics section in the
corresponding datasheet.
1.3 Reset
This section describes the three types of reset on microcontrollers of the STM32C0 series, namely power reset,
system reset and RTC domain reset.
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1.3.1 Power reset
A power reset is generated when one of the following events occurs:
• power-on reset (POR) or brown-out reset (BOR)
• exit from Standby mode
• exit from Shutdown mode
Power and brown-out reset set all registers to their reset values.
When exiting Standby mode, all registers in the VCORE domain are set to their reset value. Registers outside the
VCORE domain (back up register, WKUP, IWDG, and Standby/Shutdown mode control) are not impacted.
When exiting Shutdown mode, the brown-out reset is generated, resetting all registers.
1.3.2 System reset
System reset sets all registers to their reset values, except for the reset flags in the RCC control/status register 2
(RCC_CSR2) and the registers in the RTC domain.
System reset is generated when one of the following events occurs:
• low level on the NRST pin (external reset)
• window watchdog event (WWDG reset)
• independent watchdog event (IWDG reset)
• software reset (SW reset)
• low-power mode security reset
• option byte loader reset
• power-on reset
The reset source can be identified by checking the reset flags in the RCC_CSR2 register.
NRST pin (external reset)
Through specific option bits, the NRST pin is configurable to operate as:
•Reset input/output (default at device delivery)
Valid reset signal on the pin is propagated to the internal logic. Each internal reset source is led to a pulse
generator, whose output drives this pin. The GPIO functionality (PF2) is not available. The pulse generator
guarantees a minimum reset pulse duration of 20 μs for each internal reset source to be output on the
NRST pin. An internal reset holder option can be used, if enabled in the option bytes, to ensure that the
pin is pulled low until its voltage meets VIL threshold. This function makes possible the detection of internal
reset sources by external components when the line faces a significant capacitive load.
•Reset input
In this mode, any valid reset signal on the NRST pin is propagated to the device internal logic. Resets
generated internally by the device are not visible on the pin. In this configuration, GPIO functionality (PF2)
is not available.
•GPIO
In this mode, the pin can be used as PF2 standard GPIO. The reset function of the pin is not available.
Reset is only possible from device internal reset sources and it is not propagated to the pin.
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Figure 3. Simplified diagram of the reset circuit
External
reset
VDD
RPU
Internal
reset sources
NRST
System reset
Filter
Pulse
generator
(min 20 μs)
D Q
CLEAR
Bidirectional
reset
Reset holder
Note: Upon power reset or wake up from shutdown mode, the NRST pin is configured as Reset input/output and
driven low by the system until it is reconfigured to the expected mode when the option bytes are loaded, in the
fourth clock cycle after the end of trstempo.
Software reset
The SYSRESETREQ bit in the Cortex®-M0+ application interrupt and the reset control register must be set to
force a software reset on the device (refer to the programming manual PM0223).
Low-power mode security reset
To prevent critical applications from mistakenly enter a low-power mode, three low-power mode security resets
are available. If enabled in option bytes, the resets are generated in the following conditions:
•Entering Standby mode
This type of reset is enabled by resetting nRST_STDBY bit in user option bytes. In this case, whenever
a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby
mode.
•Entering Stop mode
This type of reset is enabled by resetting nRST_STOP bit in user option bytes. In this case, whenever a
Stop mode entry sequence is successfully executed, the device is reset instead of entering Stop mode.
•Entering Shutdown mode
This type of reset is enabled by resetting nRST_SHDW bit in user option bytes. In this case, whenever a
Shutdown mode entry sequence is successfully executed, the device is reset instead of entering Shutdown
mode.
Option byte loader reset
The option byte loader reset is generated when the OBL_LAUNCH bit (bit 27) is set in the FLASH_CR register.
This bit is used to launch the option byte loading by software.
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1.3.3 RTC domain reset
The RTC domain has two specific resets. An RTC domain reset is generated when one of the following events
occurs:
• software reset, triggered by setting the RTCRST bit in the register RCC_CSR1
• VDD power on
An RTC domain reset only affects the LSE oscillator, the RTC, and the register RCC_CSR1.
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2Clocks
The microcontrollers of the STM32C0 series provide the following clock sources producing primary clocks:
•HSI48 RC, a high-speed fully integrated RC oscillator producing HSI48 clock (48 MHz)
•HSE OSC, a high-speed oscillator with external crystal/ceramic resonator or external clock source,
producing HSE clock (4 to 48 MHz)
•LSI RC, a low-speed fully integrated RC oscillator producing LSI clock (about 32 kHz)
•LSE OSC, a low-speed oscillator with external crystal/ceramic resonator or external clock source,
producing LSE clock (accurate 32.768 kHz or external clock up to 1 MHz)
•I2S_CKIN, a pin for direct clock input for the I2S1 peripheral
Each oscillator can be switched on or off independently when it is not used, to optimize power consumption.
Check the subsections of this section for more functional details. For electrical characteristics of the internal and
external clock sources, refer to the device datasheet.
The device produces secondary clocks by dividing or/and multiplying the primary clocks:
•HSISYS, a clock derived from HSI48 through division by a factor programmable from 1 to 128.
•SYSCLK, a clock obtained through selecting one of the LSE, LSI, HSE, and HSISYS clocks.
•HSIKER, a clock derived from HSI48 through division by a factor programmable from 1 to 8.
•HCLK, a clock derived from SYSCLK through division by a factor programmable from 1 to 512.
•HCLK8, a clock derived from HCLK through division by eight.
•PCLK, a clock derived from HCLK through division by a factor programmable from 1 to 16.
•TIMPCLK, a clock derived from PCLK, running at PCLK frequency if the APB prescaler division factor is
set to 1, or at twice the PCLK frequency otherwise.
Additional secondary clocks are generated by fixed division of HSE, HSI48, and HCLK clocks.
The HSISYS is used as a system clock source after startup from reset, with the division by four (producing 12
MHz frequency).
The HCLK clock and PCLK clock are used for clocking the AHB and the APB domains, respectively. Their
maximum allowed frequency is 48 MHz.
The peripherals are clocked with the clocks from the bus that they are attached to (HCLK for AHB, PCLK for APB)
except:
•TIMx, with:
– TIMPCLK running at PCLK frequency if the APB prescaler division factor is set to 1, or at twice the
PCLK frequency otherwise
•USARTx, with these clock sources to select from:
– SYSCLK (system clock)
– HSIKER
– LSE
– PCLK (APB clock)
The wake-up from Stop mode is supported only when the clock is HSI48 or LSE.
•ADC, with these clock sources to select from:
– SYSCLK (system clock)
– HSIKER
The wake-up from Stop mode is supported only when the clock is HSI48.
•I2Cx, with these clock sources to select from:
– SYSCLK (system clock)
– HSIKER
– PCLK (APB clock)
The wake-up from Stop mode is supported only when the clock is HSI48.
•I2Sx, with these clock sources to select from:
– SYSCLK (system clock)
– HSIKER
– I2S_CKIN pin
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•RTC, with these clock sources to select from:
– LSE
– LSI
– HSE clock divided by 32
The functionality in Stop mode (including wake-up) is supported only when the clock is LSI or LSE.
•IWDG, always clocked with LSI clock.
•SysTick (Cortex® core system timer), with these clock sources to select from:
– HCLK (AHB clock)
– HCLK clock divided by 8
The selection is done through SysTick control and status register.
HCLK is used as Cortex®-M0+ free-running clock (FCLK). For more details, refer to the programming manual
PM0223.
Figure 4. Clock tree
DT66111V2
MCO
LSCO
async clock
to ADC
to IWDG
to RTC
to PWR
HCLK
to AHB bus, core, memory and DMA
FCLK Cortex free-running clock
to Cortex system timer
to APB peripherals
PCLK
to I2S1
LSE
SYSCLK
to USART1
to I2C1
I2S_CKIN
OSC32_OUT
OSC32_IN
LSI
LSE
HSE
SYSCLK
HSE
HSISYS SYSCLK
OSC_OUT
OSC_IN
LSI RC
32 kHz
HSIKER
HSIKER
LSE
LSI
/32
AHB PRESC
/ 1,2,4,..,512
/ 1,2,…,128
HSE OSC
4-48 MHz
Clock
detector
APB
PRESC
/ 1,2,4,8,16
/ 8
LSI
HSE
LSE
SYSCLK
I2S_CKIN
SYSCLK
SYSCLK
BOLD: clock origin
LSE
LSI
LSE
LSI
HSE
PCLK
PCLK
HSISYS
HCLK8
LSE OSC
32.768 kHz
Clock
detector
HSI48 RC
48 MHz
HSI48
HSI48
MCO2(2)
/ 1,2,…,128
HSIKER
HSIKER
HSIKER
to TIM1/3/
14/16/17
x1, x2
TIMPCLK
/1,2,4,…,128
/1,2,3,…,8
RTCCLK
(1)
(1) TIMPCLK is running at PCLK frequency if the APB prescaler division factor is set to 1, or at twice the PCLK
frequency otherwise
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2.1 HSE clock
The high speed external clock signal (HSE) can be generated from two possible clock sources:
• HSE external crystal/ceramic resonator
• HSE user external clock
The resonator and the load capacitors must be placed as close as possible to the oscillator pins to minimize
output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the
selected oscillator.
Figure 5. HSE / LSE clock sources
External crystal/ceramic resonator (HSE crystal)
The 4 to 48 MHz external oscillator has the advantage of producing a very accurate rate on the main clock.
The associated hardware configuration is shown in Figure 5. Refer to the electrical characteristics section of the
datasheet for more details.
The HSERDY flag in the clock control register (RCC_CR) indicates if the HSE oscillator is stable or not. At
startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the
clock interrupt enable register (RCC_CIER).
The HSE crystal can be switched on and off using the HSEON bit in the clock control register (RCC_CR).
External source (HSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to 48 MHz. This
mode is selected by setting the HSEBYP and HSEON bits in the clock control register (RCC_CR). The external
clock signal (square, sinus, or triangle) with around 40 to 60% duty cycle depending on the frequency (refer to
the datasheet) must drive the OSC_IN pin, on devices where OSC_IN and OSC_OUT pins are available (see
Figure 5).
The OSC_OUT pin can be used as a GPIO or it can be configured as OSC_EN alternate function, to provide
an enable signal to the external clock synthesizer. It makes possible to stop the external clock source when the
device enters low power modes.
Note: For details on pin availability, refer to the pinout section in the corresponding device datasheet.
To minimize the consumption, it is recommended to use the square signal.
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