Sony IT-B1 User manual

SERVICE MANUAL

SPECIFICATIONS

Dial signal Tone, 10 PPS (pulse) selectable

Dimensions Approx. 69 ×74.5 ×225 mm (w/h/d)

(Approx. 2 3/4 ×3 ×8 7/8 inches)

Mass Approx. 485 g

(Approx. 17 oz), attachments included

Supplied accessories • Telephone line cords (2)

• Handset cord

Design and specifications are subject to change without notice.

IT-B1

Canadian Model

Central & South America Model

TELEPHONE

MICROFILM

Notes on Chip Component Replacement

•Never reuse a disconnected chip component.

•Notice that the minus side of a tantalum capacitor may be dam-

aged by heat.

Photo: WHITE Type

IT-B1

3-2. SCHEMATIC DIAGRAM — HANDSET SECTION — • Refer to page 7 for IC Block Diagrams.

Note:

• All capacitors are in µF unless otherwise noted. pF: µµF

50 WV or less are not indicated except for electrolytics

and tantalums.

• All resistors are in Ωand 1/4W or less unless otherwise

specified.

• % : indicates tolerance.

•¢: internal component.

•C: panel designation.

•U: B+ Line.

• Connect J2 and J3 with handset cord.

Power voltage is dc 12V and fed with regulated dc power

supply from J3 with 100 Ωin series.

• Voltage is dc with respect to ground under no-signal

condition.

no mark : OFF HOOK

( ) : ON HOOK

• Voltages aretaken withaVOM(Inputimpedance 10MΩ).

Voltage variations may be noted due to normal produc-

tion tolerances.

• Signal path.

N: RX (fromTEL LINE)

O:TX (to TEL LINE)

P: bell

• Abbreviation

MX : Mexican model

LA : Latin American model

3-4. SCHEMATIC DIAGRAM — CRADLE SECTION —

IT-B1

3-3. PRINTED WIRING BOARD — CRADLE SECTION —

Note:

• All capacitors are in µF unless otherwise noted. pF: µµF

50 WV or less are not indicated except for electrolytics

and tantalums.

• All resistors are in Ωand 1/4W or less unless otherwise

specified.

• % : indicates tolerance.

•¢: internal component.

•C: panel designation.

•U: B+ Line.

• Power voltage is dc 12V and fed with regulated dc power

supply from J3 with 100 Ωin series.

• Voltage is dc with respect to ground under no-signal

condition.

no mark : OFF HOOK

( ) : ON HOOK

• Voltages aretakenwith aVOM(Input impedance10 MΩ).

Voltage variations may be noted due to normal produc-

tion tolerances.

• Signal path.

N: RX (fromTEL LINE)

O:TX (to TEL LINE)

P: bell

Note:

•X: parts extracted from the component side.

•¢: internal component.

•b: Pattern from the side which enables seeing.

(The other layer’s patterns are not indicated.)

D33 D-2

D34 D-1

IC1 B-2

ZD1 B-1

D1 A-3

D2 A-3

D3 A-3

D4 B-3

D5 B-1

D31 C-2

D32 C-1

• Semiconductor Location

Ref. No. Location Ref. No. Location

• IC Block Diagrams

IC2 TEA1112AT

IC3 HM91510AP

CURRENT

REFERENCE

LOW

VOLTAGE

CIRCUIT

LED

DRIVER ATT

MICRO

MUTE

AGC

CIRCUIT

VCC

LN 2

SLPE 3

LED 4

REG 5

GAS 6

MMUTE 7

OTMF 8

MUTE

GAR QR VEE MIC+ MIC- IRAGC

15 14 13 12 11 910

ROW

INTERFACE CIRCUIT

COLUMN

INTERFACE CIRCUIT DIVIDER

OSC

KERNEL CONTROL CIRCUIT

INPUT

INTERFACE

CIRCUIT

OUTPUT

INTERFACE

CIRCUIT

ROW/COLUMN

PROGRAMMING

COUNTER

D/A

CONVERTER

DECODER

DATA LATCH

PULSE

GENERATOR

LNB

MEMORY

C1 2

C2 3

C3 4

VSS

VDD

KT 6

OSCI 7

OSCO 8

XMUTE 9

VSS

R4 17

R3 16

R2 15

R1 14

MODE 1213

TONE 10

VDD

HKSPO

MEMORY

VDD

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