Sony HST-SE581 User manual

HST-SE581

AEP Model

E Model

Australian Model

SERVICE MANUAL

CASSETTE DECK RECEIVER

MICROFILM

ManufacturedunderlicensefromDolbyLaboratories

Licensing Corporation.

“DOLBY” and the double-D symbol aand “PRO

LOGIC” are trademarks of Dolby Laboratories

Licensing Corporation.

•Thissetisthe tunerdeck andamplifier

section in SEN-T481.

SPECIFICATIONS

Tape deck Model Name Using Similar Mechanism HST-471

Section Tape Transport Mechanism Type TCM-220WR2

— Continued on next page —

Tuner section

FM stereo, FM / AM superheterodyne tuner

FM tuner section

Tuning range 87.5 – 108.0 MHz

Antenna FM leadantena

Antenna terminals 75 Ωunbalanced

Intermediate frequency 10.7 MHz

AM tuner section

Tuningrange

European model: 531 – 1,602 kHz

Other models: 531 – 1,602 kHz (with the interval set at

9 kHz)

530 – 1,710 kHz (with the interval set at

10kHz)

Antenna AM loop antenna, outdoor antenna

terminals

Intermediate frequency450 kHz

Amplifier section

European models:

(FRONT)

DIN power output 90 + 90 W

(at rear / center / woofer off at 1 kHz, 8 Ω)

Continuous RMS power output

110 + 110 W

(at rear / center / woofer off at 1 kHz,

10% THD, 8 Ω)

70 W / ch

(at SURROUND ON at 1 kHz,

10% THD, 8 Ω)

(REAR) 40 W

(at front / center / woofer off at 1 kHz, 8 Ω)

(CENTER) 40 W

(at front / rear / woofer off at 1 kHz, 8 Ω)

(WOOFER) 70 W

(at front / rear / center off at 40 Hz, 4 Ω)

Other models:

Peak music power output 1,600 W (total)

(FRONT)

Continuous RMS power output

90 + 90 W

(at rear / center / woofer off at 1 kHz,

10% THD, 8 Ω)

(REAR) 40 W

(at front / center / woofer off at 1 kHz, 8 Ω)

(CENTER) 40 W

(at front / rear woofer off at 1 kHz, 8 Ω)

(WOOFER) 70 W

(at front /rear/ center off at 40 Hz, 4 Ω)

Inputs

PHONO (phono jacks):

sensitivity 2.5 mV, impedance 50 kΩ

CD (phono jacks): sensitivity 400 mV, impedance 50 kΩ

VIDEO1, 2 (phono jacks):

sensitivity 250 mV, impedance 50 kΩ

HST-SE581

— 13 — — 14 —

5-3. SCHEMATIC DIAGRAM — MAIN SECTION (1/2) — • See page 10 for Waveforms. • See page 39 for IC Block Diagrams.

HST-SE581

— 15 — — 16 —

5-4. SCHEMATIC DIAGRAM — MAIN SECTION (2/2) — • See page 39 for IC Block Diagrams.

HST-SE581

— 21 — — 22 —

5-7. SCHEMATIC DIAGRAM — DISPLAY SECTION — • See page 10 for Waveforms. • See page 41 for IC Pin Function.

HST-SE581

— 25 — — 26 —

5-9. SCHEMATIC DIAGRAM — SW SECTION —

DOLBY NR

1/u

HST-SE581

— 29 — — 30 —

5-11. SCHEMATIC DIAGRAM — POWER AMP SECTION — • See page 39 for IC Block Diagrams.

HST-SE581

— 33 — — 34 —

5-13. SCHEMATIC DIAGRAM — DECK SECTION — • See page 39 for IC Block Diagrams.

HST-SE581

— 37 — — 38 —

5-15. SCHEMATIC DIAGRAM — POWER TRANSFORMER SECTION —

EXCEPT

E MODEL

EXCEPT

E MODEL

HST-SE581

— 39 — — 40 —

5-16. IC BLOCK DIAGRAMS

IC300 LV1041M (MAIN BOARD)

IC302 LC7822 (MAIN BOARD)

IC401 LC75373ED (MAIN BOARD)

IC502 LB1641 (MAIN BOARD)

2928

3736

7475

80 72 65

6970

STRIM

OSC

VOL

VCA VCA P

VCA VCA

VCA VCA VCA VCA

IEV

NOISE

GEN

NOISE

FILTER

BPF

CONTROL

BPF

V REF

STRIM

MODE

RECT

CUT

B NR

OUT

FILTER

DATA

DECODER

VOL/

MUTE

BPF

RECT

LOGIC

FF RECT

C MODE

LOGIC LOGIC

MASTER

VOL

PPB

MASTER VOL

VDD

PCM

CONTROL

SRAM

FILTER

R BPF2

R BPF1

S DC OUT

C DC OUT

R DC OUT

L DC OUT

V REF

VCC

C OUT

S OUT

R OUT

L OUT

GND

L IN

R IN

S IN

DELAY OUT

C VOL IN

DET

IREF

R OUT

R NF

L NF

L OUT

L BPF2

L BPF1

RT IN

LT IN

DC CUT

C MODE

GND

NS BPF1

OSC

NS BPF2

ENABLE

DATA

CLK

DATA

CLK

ENABLE2

VSS

OSC

VDD

A/D

D/A

DC CUT

VCC

C VOL OUT

C OP IN

GND

C OP NF

C OP OUT

VOL REF

S OP OUT

S OP NF

S OP IN

S VOL OUT

L RECT

DC CUT4

R RECT

DC CUT3

L BPF3

VLR TH

VLR 1

VLR 2

VCS 2

VCS 1

VCS TH

L+R RECT

DC CUT2

L-R RECT

DC CUT1

R DET3

OP VREF

S VOL IN

S OUT

DC CUT

CONTROL

LATCH

SHIFT RESISTOR

LEVEL SHIFT

VEE

OUT

VSS

RESET

VDD

OUT

ININ

OUT

–

–+

–

–+

–

DECODER LATCH SHIFT

–

12 3 45 6 7 8 9 10

2324252627282930313233

LSELO

VDD

RSELO

RVRIN

RCOM

RT1

RT2

RT3

RTOUT

RSIN

RS1

RS2

RS3

RSOUT

RFIN

RFOUT

RROUT

VSS

VREF

LROUT

LFOUT

LFIN

LSOUT

LS3

LS2

LS1

LSIN

LTOUT

LT3

LT2

LT1

LCOM

LVRIN

12 3 45 6 7 8 9 10

GND

MOTOR

DRIVE

NOISE

FILTER

CLAMP

FWD.IN

REV.IN

VCC 1

VCC 2

NOISE

FILTER

MOTOR

DRIVE

MOTOR

DRIVE

MOTOR

DRIVE

T.S.D O.C.P

FWD/REV/STOP

CONTROL LOGIC



TR3 R1

TR4

TR6

TR7

TR5

TR1

TR2

D4 D3

TR8

D1 D2 R5

INPUT

-VEOUT

+VEOUT

GND

SUB

12345 6 7 8 9

INVERTER

COMPARATER

SW R1 GND SW P1 CONT GND VCC SW P2 GND SW R2

235

46798

MUTE

+ VOUT1

– VOUT1

COMP1

MF1

IN1

GND

IN2

NF2

COMP2

– VOUT2

+ VOUT2

VCC1

VCC2

VEE

PROTECTOR

BIAS CIRCUIT

REG DRIVE PRE

DRIVE

10 12 13 1514

DRIVE

PRE

DRIVE

IC602 UPC1330HA (AUDIO BOARD)

IC151 UPC2581V (POWER BOARD)

IC651 STK350-230 (POWER BOARD)

— 39 —

5-16. IC BLOCK DIAGRAMS

IC300 LV1041M (MAIN BOARD)

2928

3736

7475

80 72 65

6970

STRIM

OSC

VOL

VCA VCA P

VCA VCA

VCA VCA VCA VCA

IEV

NOISE

GEN

NOISE

FILTER

BPF

CONTROL

BPF

V REF

STRIM

MODE

RECT

CUT

B NR

OUT

FILTER

DATA

DECODER

VOL/

MUTE

BPF

RECT

LOGIC

FF RECT

C MODE

LOGIC LOGIC

MASTER

VOL

PPB

MASTER VOL

VDD

PCM

CONTROL

SRAM

FILTER

R BPF2

R BPF1

S DC OUT

C DC OUT

R DC OUT

L DC OUT

V REF

VCC

C OUT

S OUT

R OUT

L OUT

GND

L IN

R IN

S IN

DELAY OUT

C VOL IN

DET

IREF

R OUT

R NF

L NF

L OUT

L BPF2

L BPF1

RT IN

LT IN

DC CUT

C MODE

GND

NS BPF1

OSC

NS BPF2

ENABLE

DATA

CLK

DATA

CLK

ENABLE2

VSS

OSC

VDD

A/D

D/A

DC CUT

VCC

C VOL OUT

C OP IN

GND

C OP NF

C OP OUT

VOL REF

S OP OUT

S OP NF

S OP IN

S VOL OUT

L RECT

DC CUT4

R RECT

DC CUT3

L BPF3

VLR TH

VLR 1

VLR 2

VCS 2

VCS 1

VCS TH

L+R RECT

DC CUT2

L-R RECT

DC CUT1

R DET3

OP VREF

S VOL IN

S OUT

DC CUT

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