SCHLAPPI ENGINEERING NIBBLER User manual
NIBBLER MANUAL
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Technical Information 3
Voltage Levels 3
Current Draw 3
Module Description and Features 4
Introduction 4
Controls 5
Inputs 5
Outputs 6
Indicators 6
Block Diagram 7
How It Works 7
Binary and Accumulators 7
Synchronous/Asynchronous Operation 8
Phase Oset Switches 9
Waveforms 10
Patches to start exploring with: 11
Clock Divider 11
Clock Divider Drum Sequencer 11
Frequency Divider (or Subharmonic Generator) 12
Triangle Wave 12
Shift Register Noise 13
Rungler Variant 13
Simple Benjolin Variant 14
Sequencer (or Arpeggiator) 15
Phase Oset Sequences 15
Cross Patched Nibblers 16
Chaining Nibblers 16
Contact Info: 17
Technical Information
Voltage Levels
The Nibbler is designed for compatibility with Eurorac voltage standards. Inputs and
outputs are voltage and current protected and should not but damaged by any level
within the Eurorac ecosystem (-12V to +12v, or 24v pea to pea ).
Current Draw
+12V: 37mA
-12V: 17mA
SIGNAL TYPE LEVEL Notes
Gate outputs 0 or 10V
Stepped outputs 0 to 10V
Gate inputs 2.8V
threshold
Comparator input stage triggers around
2,8V
Module Description and Features
Introduction
The Nibbler is a four bit digital accumulator based on CMOS logic. What this means is that
it counts in binary from zero to fteen, with inputs and outputs for individual bits as well as
stepped voltage outputs (digital to analog converters). It does this with individual logic
chips instead of a CPU.
The concept here is that counting in binary (and its expression in bits) is inherently musical,
and we can use it to create both rhythms and modulation voltages (or melodies).
The interface is designed to to be playable, with switches for the binary counting as well as
two mode switches and two phase oset switches (so the second stepped analog output
can be oset in phase from the rst). There is also a large Cherry MX Brown eyboard
switch for resetting the register to zero.
Controls
Switches
Button
All the other inputs are aected by the ASYNC/SYNC control to either only have an
aect on the rising edge of the clock or immediately.
These inputs control the rate of counting.
These are the shift register inputs. The ASYNC/SYNC control similarly aects whether it will
shift only on a cloc or any time a pulse is received.
Inputs
All inputs are logic inputs with a threshold of around 2.8V that trigger on the rising
edge.
CONTROL DESCRIPTION
ADD 8 Adds 8 to the register
ADD 4 Adds 4 to the register
ADD 2 Adds 2 to the register
ADD 1 Adds 1 to the register
SUBTRACT/
ADD
Determines if the number formed by the ADD SWITCHES is added or
subtracted from the number already in the register
ASYNC/
SYNC
Determines if the output is updated only on a rising clock pulse (SYNC)
or every time an input is received (ASYNC)
OFFSET These two switches together set a phase oset for the second stepped
voltage. It can be 0º (both down), 45º (only bottom switch up), 90º (only
top switch up), or 180º (both switches up)
OFFSET
INPUT Description
CLOCK Clock input, also used for audio rate frequency division purposes.
Necessary for most operations.
RESET Clears the register, setting all outputs to 0, AC coupled so it can be
used as a hard sync input at audio rate
SUB This input interacts with the SUBTRACT ADD switch to change the
state to the opposite of the current setting.
INPUT Description
CARRY IN Intended for chaining multiple Nibblers, to make a larger register by
patching a CARRY OUT to a carry in. Eectively the same as GATE
1.
GATE 1 Adds with the ADD 1 switch to set the rate of counting.
GATE 2 Adds with the ADD 2 switch to set the rate of counting.
GATE 4 Adds with the ADD 4 switch to set the rate of counting.
GATE 8 Adds with the ADD 5 switch to set the rate of counting.
INPUT Description
SHIFT While SHIFT is high in SYNC mode any clock pulse will shift the
contents of the register up one, or if in ASYNC mode it will shift on
any pulse on this input.
SHIFT DATA Replaces the input of the shift register. With no input the top bit
(OUT *)cycles around and enters from bottom.
DATA XOR Performs an XOR function with whatever data is at the input to the
shift register
CONTROL DESCRIPTION
RESET Clears the register, setting all outputs to 0
Outputs
Gate outputs are either 0 or approximately 10V
Analog stepped voltages output 0 to 10V
Indicators
All inputs and outputs have blue LEDs indicating their current state, at audio rate they
may show a solid blue. The reset button also has an LED underneath it.
LABEL NAME DESCRIPTION
STEPPED
OUT 1
A weighted sum of the register bits as a stepped analog
voltage
STEPPED
OUT 2
The register bits summed with the two oset switches to
create a static phase oset
NAME DESCRIPTION
CARRY The CARRY out goes high for one clock pulse when the register
overows. You can use this to chain additional Nibblers for a bigger
register, or as another gate output. This is probably the output to
use if you are using Nibbler as a clock divider.
OUT 8 Gate output for the top bit of the register, which represents 8
OUT 4 Gate out put for the register bit that represents 4
OUT 2 Gate output for the register bit that represents 2
OUT 1 Gate output for the bottom bit of the register, which represents 1
Block Diagram
How It Works
The combination of switches and gate are the input for a 4 bit binary word. This will
be a number between 0 and 15. This is added to the number already present in the
register (a 4 bit memory unit) and then stored back in the register. This conguration
of an adder and a register is known as an accumulator.
Accumulators are a fundamental digital building block and have many interesting
properties, one of which is that it is the digital equivalent of an integrator (the
mathematical operation) and is a big part of most lter or oscillator designs.
This particular register also has a bit shifting operation built in, which rotates the bits
from lowest to highest at each clock pulse while shift is high (in synchronous mode).
Binary and Accumulators
Binary is a number representation which only uses ones and zeros, and each
position corresponds to a power of two. With a four bit word we have 1, 2, 4, and 8,
which together can add up to 15.
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
1
3
0
0
1
0
2
0
1
0
1
5
0
1
0
0
4
0
1
1
1
7
0
1
1
0
6
1
0
0
1
9
1
0
0
0
8
1
0
1
1
11
1
0
1
0
10
1
1
0
1
13
1
1
0
0
12
1
1
1
1
15
1
1
1
0
14
If the number in the register goes above 15 it overows and wraps around. For
example if there is 14 in the register and you add 4 then the new value will be 2. You
can think of this as a modulo 16 operation.
This has two cool properties: One is that if you are counting by one, then each higher
bit will be half the frequency as the previous one, allowing for use as a clock divider
or octave down eect. The other is that if you increment the counter (accumulator) by
an odd number, then you will get a waveform (or sequence) that will keep wrapping
around with an oset and take some time to repeat. See the waveforms page.
Synchronous/Asynchronous Operation
The “SYNC / ASYNC” switch determines if the output is taken from the register, which
will update only on a rising clock pulse, or from the adder which will change
immediately. This can be useful for wonky patterns or changing the audio rate eect.
For clean sounding rhythms and modulation it probably makes sense to keep this
switch set to SYNC, however at audio rate you can think about modulating the gate
inputs as frequency modulation. Frequency modulation inherently lters modulation
close to or above the carrier (in this case the clock signal).
In the ASYNC mode (taking the output from the asynchronous adder) then you will be
getting a combined phase and frequency modulation eect at lower modulation
frequencies and at higher frequencies the phase modulation will dominate. At audio
rate which one you want will probably be determined by whether you want that lter
eect or not, try both!
See the Three Body manual for more about phase and frequency modulation. The
same principles all apply here, except the clock input of the Three Body’s oscillators
is a xed 12.5MHz and the accumulator is 36 bits deep. This allows for many orders
of magnitude higher precision and delity, however the point here is to interact with
the bits directly.
The ASYNC mode also has a somewhat unusual normalization, the SHIFT and
CLOCK inputs are XOR’ed together and sent to the clock of the shift register.
This means that in ASYNC mode you do not need to use the CLOCK input to use the
SHIFT input, making the shift register functionality independent of the accumulator
functionality. This can then be used for a Rungler patch as detailed in the patch
section of the manual.
14 + 4 = 18 - 16 = 2
Phase Oset Switches
The two oset switches can be used to create a second stepped voltage oset in
phase. The four osets are shown below. At audio rate this won’t make much of a
dierence (unless you are doing oscillographics) but at LFO rate for modulation this
can be used so one sequence is at it’s highest value when the other is at its lowest
(180 degrees) or oset just slightly (45 degrees) or 90 degrees o.
The intention here was to have two modulation voltages for use with the Three Body
and other stereo processes. It would also make a lot of sense to feed into a
multichannel quantizer and get and eect of multiple melody lines following each
Lower oset
switch
Upper oset
switch
Degree
oset
Numerical
oset
down down 0 0
up down 45 2
down up 90 4
up up 180 8
Longer sequences can be created by modulating the gate inputs.
The SUBTRACT switch (and related gate input) alters the direction of counting. If you
look at the waveforms page you will see that that can also be achieved by changing
the frequency word (setting of the switches). In this case they are primarily intended
as performance controls to allow for more dynamic sequences.
0001110011100011
0010110100101101
0110011001100110
0101010101010101
0
0
1
1
0
1
0
0
0011001100110011
0101010101010101
0000000000000000
0001000100010001
0011011011001001
0101101001011010
0011001100110011
0101010101010101
0
1
0
1
0010110100101101
0110011001100110
0101010101010101
0000000000000000
0
1
1
0
0000111100001111
0011001100110011
0101010101010101
0000000000000000
0
0
1
0
0010101011010101
0111100001111000
0110011001100110
0101010101010101
0
1
1
1
0101010101010101
0000000000000000
0000000000000000
0000000000000000
1
0
0
0
0101010110101010
0000111100001111
0011001100110011
0101010101010101
1
0
0
1
0000000011111111
0000111100001111
0011001100110011
0101010101010101
0
0
0
1
0111111110000000
0111100001111000
0110011001100110
0101010101010101
1
1
1
1
0100100110110110
0010110100101101
0110011001100110
0101010101010101
1
0
1
1
0101100101011001
0011001100110011
0101010001010100
0000000000000000
1
0
1
0
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0
0
0
0
0111100001111000
0110011001100110
0101010101010101
0000000000000000
1
1
1
0
0110011001100110
0101010101010101
0000000000000000
0000000000000000
1
1
0
0
0110001110001100
0101101001001010
0011001100100011
0101010101010101
1
1
0
1
Waveforms
The four switches of the nibbler can be thought of as dening 16 states, waveforms, or
sequences (depending on how you are using it). They are shown below (counting up, from
left to right) along with the binary representation (which would also mirror the gate
outputs).
You can see that counting by zero yields nothing, while counting by one creates a rising
ramp, counting by fteen creates a falling ramp, and the waveforms in between are
mirrored around counting by 8, which creates a series of pulses at half of full-scale
amplitude and half the rate of the incoming cloc .
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