Roland SDE-1000 Operating and maintenance manual

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3

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1

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FEB.

6,1984

SDE-1000/3000

SDE-1000

3000

First

Edition

ISDE-3000

|

Front

LED

SLB-26URS

RED

(15029132)

LEDSLB-26UR5

RED

(15029132)

pPot

K1611008FE-100KB

(13219361)

LEDGL9ND2

Knob

ORN

RED/GRN

(2247025900)

(15029148)

PHOTO

SDE-3000

SPECIFICATIONS

Button

'(2247053700)

LEDSLB-26YYHLYEL

(1S029159)

LED

GL-9HD12

RED

(15029152)

L-

LED

SLB

26GG5F

GRN

(15029158)

Display

panel

(2221071300)

Button

(2247054700)

Control

panel

(2221031100)

Button

\

LED

GL-3AR1

RED

(2247054200)

\

(15029110)

Button

Button

Fluorescent

display

FIP16A5R

(2247054300)

(2247057700)

(15029710)

Button

(2247054100)

Power

Switch

SDG

A

3P

(13129124)

Button

(2247024000)

Rear

GND

terminal

(13459123)

Rear

panel

(2221031300)

Pot.

EVH-6PA361B54

(13219214)

Knob

(2247023900)

Jack

HU

531701-100

(13449240)

6

\

Bushing

BU4801

(12369511)

Jack

HLJ

531701-010

(13449238)

ISDE-10001

Front

LEDSLB-26YYHLYEL

(15029159)

LED

SLB-26UR5

RED

(15029132)

Pot.

K1611008FE

100KD

(13219361)

Knob

ORN

(2247025900)

Pot.

K1611008FE

50KB

(13219360)

Knob

GRN

(2247026000)

Pot.

K1611008FE

50KA

(13219359)

Knob

BLU

(2247026200)

Button

(2247054500)

Jack

HLJ

5317

01-030

(13449239)

LEDGL-9HD12

RED

(15029152)

Button

(2247053500)

Switch

SUF-12

(13129338)

Display

panel

(2221071400)

LED

SLB

26GG5F

GRN

(15029158)

Pot.

K1611008FE

50KB

(13219360)

Knob

YE

L

(2247026100)

Pot.

K1611008FE

50KB

(13219360)

Knob

BLU

(2247026200)

Button

(2247053700)

Button

(2247053800)

Fluorescent

display

LED

GL-3AR1

RED

FIP5A8B

(15029110)

(15029709)

\

\

Conrol

panel

(2221031200)

Power

Switch

SDGA

3P

(13129124)

Button

(2247024000)

Button

(2247054000)

Rear

GND

terminal

(13459123)

Bushing

BU4801

(12369511)

SDE-1000/3000

FEB.

5,1984

12

3

4

5

6

EXPLODED

VIEW

SDE-1000/3000

7

8

9

10

11

\2

13

14

16

17

21

22 2H

24 2^

2b

4x8

BLK

binding-^

M4

internal

tooth

3x8

BLK

binding

3x6

BLK

binding

4x12

BLK

oval

3x8

BLK

binding

f

4x12

BLK

oval

(1000):

SDE-1000,

(3000):

SDE-3000

Control

panel

2221031200

2221031100

-Display

panel

2221071400

2221071300

-Fluorescent

display

15029709

FIP5A8B

15029710

(4)-Switch

board

7411608005

7411708005

(s)

-PCB

holder

221903JB01

Q*y~

Button

assembly

2247090300

2247090100

FIP16A5R

(1000)

(3000)

(1000)

(3000)

(1000)

(3000)

(1000)

(3000)

(1000)

(3000)

&■

^7

J—Button

assembly

2247090200

Button

BLK

2247024000

•-Cushion

2226022200

(jo}-LED

holder

2219031900

^Jy-Joint

A

2215040100

(12)—

Connection

rod

2214020700

(m-

Joint

B

2215040200

(i4)—

Line

cord

strain

relief

12369410

1702B

(3000)

-Main

board

7411606032

7411706026

'li

5}-Push

switch

13129338

-Button

WHT

12470514

-Push

switch

13129337

-Push

switch

13129124

--Power

board

7411609000

7411709000

• -

Insulation

sheet

2216052701

--GND

terminal

13459123

SUF-12

SUE-12

SDGA3P

FEB.

5.1984

SDE-1000/3000

PARTS

LIST

CASE

(SDE-1000)

(SDE-1000)

(SDE-1000)

(SDE-1000)

(SDE-1000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-1000)

(SDE-3000)

(SDE-1000)

(SDE-1000)

(SDE-1000)

(SDE-1000)

(SDE-1000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

2247054500

2247054600

2247054700

2247054800

SWITCH

Button TIME

Button DEPTH

Button

OUT

Button

RATE

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

reed

relay

(SDE-3000)

JACK

13449238

13449239

13449240

HLJ5317-01-010

HLJ5317-01-030

HLJ5317-01-100

TRANSFORMER

22450348N0

22450349D0

22450350N0

22450351D0

COIL

100/117V

220/240V

100/117V

220/240V

(SDE-1000)

(SDE-1000)

(SDE-3000)

(SDE-3000)

2244023800

2244023900

12449236

PCB

LPF

S097624

LPF

S097623

OSC

S097614

LI

(SDE-3000)

7411606032

7411607001

7411608005

7411706026

7411707001

7411708005

7411709000

7411711002

Main

board

LED

board

Switch

board

Main

board

LED

board

Switch

board

Power

supply

board

(pcb

2291058201)

(pcb

2291058300)

(pcb

2291058400)

(pcb

2291057901)

(pcb

2291058000)

(pcb

2291058100)

(pcb

2291058500)

Fuses,

Fuse

labels,

capacitor

Cl

excluded.

Specify

model

and

line

voltage

when

ordering

for

complete

assy.

RAM

board

(pcb

2291083800)

Analog SW

board

(pcb

2291091900)

Substitutive

for

HI-302

and

HI-303.

No

replaceable

part.

See

P.20.

(SDE-1000)

(SDE-1000)

(SDE-1000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

POTENTIOMETER

13219361

13299101

K1611008FE

100KB

EVT-R4SA00B14

trimmer

SDE-1000/3000

FEB.

5,1984

(SDE-1000)

(SDE-1000)

(SDE-1000)

(SDE-1000)

(SDE-1000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

TRANSISTOR

15119701

15119125

15129130

15129704

15129137

15129602

15129118

2SA968-Y

2SA1115-F

2SC1583-F

2SC2238-Y

2SC2603-F

2SD667-C

2SC1923-R

(SDE-3000)

FUSE

12559105

12559510

12559504

12559506

SGA

CEE

CEE

CEE

1A

T400mA

T100mA

T160mA

100/117V

220/240V

220/240V

220/240V

(SDE-1000)

(SDE-3000)

FET

15139103

15139106

15139108

2SK30ATM-GR

2SK117-GR

2SK150-GR

(SDE-3000)

IC

15229811

15179141

15179315

15159702

15169355

15159101H0

15159104H0

15159112H0

15159133

15189111J1

15189163

15219116

15189136

15189141

15199106F0

15169102H0

15169117H0

15169356

15219108

15189152

15159115H0

1599104F0

15169301H0

15169311H0

15169332H0

15169357

15159105H0

15159129H0

15189160

15219120

15159513

15159523

15159522

15189161

15189118J0

15229802

15159316

MB63H101

MSM80C49-44RS

M5K4164NP-20

M54563

SN74LS48N

HD14001

BP

HD14011

BP

HD14049

BP

HD14174

BP

NJM311D

MB3761M

IR2E02

M5218L

NJM4562DD

yA7805UC

HD7406P

HD7407P

SN74LS628N

NE570N

NJM5534D

HD14066

BP

yA7812

UC

HD74LS00

HD74LS74P

HD74LS157P

74LS283

HD14013

BP

HD14053

BP

TDB0119

AM6012

HI-201-5

HI-302-5

HI-303-5

HA-2525-5

NJM082DR

BA662

A

TC4514

BP

DIODE

Gate

array

(Main

Controller)

CPU

64K

D-RAM

Transistor

array

7-Segments

decoder

Quad

2

Input

NOR

Quad

2

Input

NAND

Inverter

Dual

D-Flip-Flop

Comparators

Voltage

detector

LED

Driver

OP

Amp

OP

Amp

Three

Terminal

Voltage

Regulator

Hex

O.C.

Inverters

Hex

O.C.

Buffers

VCO

Compandor

OP

AMP

Analog

Switch

Three

Terminal

Voltage

Regulator

Quad

2

Input

NAND

Dual

D-Flip-Flop

2

to

1

Data

Selectors

4

bit

Binary

Full

Adders

Dual

D-Flip-Flop

Triple

2-channel

Multiplexer

Dual

Voltage

Comparator

D/A

Converter

Quad

Analog

Switch

Dual

Analog

Switch

Dual

Analog

Switch

OP

Amp

OP

Amp

VCA

4

to 16

Line

Decoder

(SDE-1000)

(SDE-1000)

(SDE-1000)

(SDE-1000)

(SDE-1000)

(SDE-1000)

(SDE-1000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

15019125

15019251

15019236

15019525

15029132

15029159

15029158

15029152

15029110

15019103

15019557

15019209T0

15029148

15029111

150192490X

1SS-133

1N4007

W-02

RD5.6EB-2

SLB-26UR5

SLB-26YYHL

SLB-26GG5F

GL-9HD12

GL-3AR1

1S-2473

RD15EB-3

S5500G

GL-9ND2

GL-3PG1

KV1226X

or

KV1226Y

(150192490Y)

Rectifier

Bridge

Zener

LED

RED

LED

YEL

LED

GRN

LED

RED

LED

RED

Zener

LED

RED/GRN

LED

GRN

Varicap

(SDE-1000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

FEB.

5,1984

SDE-1000/3000

CAPACITOR

13549884M0

13589455M0

13589456M0

13639154M0

13639194M0

13639923M0

13589139Y0

1358914OY0

13619703NA

13589138Y0

13619711N0

13639155M0

13639213M0

13639922M0

ECQM-6103MZ

ECQ-U2A103MF

ECQ-U1A103MC

ECEA1CS102

ECEA1VS102

ECEA1CN470S

YM92PS122-2A

YM92PS152-2A

CS15E1VR22K1S

YM92PS102-2A

CS15E1V4R7K1S

ECEA1CS222

ECEA1HS471

ECEA1CN100S

O.OlyF

1OOV

O.OlyF

220/240V

O.OlyF

117V

1000yF/16V

1000yF/35V

47yF/16V

O,OO12yF

O.OO15yF

0.22yFx2

O.OOlyF

4.7yF/35V

2200yF/16V

470yF/50V

10yF/16V

Polypropylene

Polypropylene

Polypropylene

Electro

Electro

Bi-polar,

electro

Polypropylene

±1%

(SDE-1OOO)

Polypropylene

±1%

(SDE-1000)

set

of

pair,

selected

(SDE-1000)

Polypropylene

±1%

(SDE-3000)

Tantalum

bead

(SDE-3000)

Electro

(SDE-3000)

Electro

(SDE-3000)

Bi-polar,

electro

(SDE-3000)

OTHERS

12389718

PX-1

11.0MHz

Xtal

2216031201

Insulation

spacer

(vinyl

sheet)

2216052701

Insulation

sheet

(fibre,

L-shaped)

2214020700

Connection

rod

2215040100

Joint

A

2215040200

Joint

B

13439127

Connector

housing

5045-11A

IIP

.13439157

Connector

housing

5045-13A

13P

2341043200

Connector

wiring

assy

IIP

2341043300

Connector

wiring

assy

13P

12569111

CR1/3N

3V

Lithium

Battery

2226022200

Cushion

2225021001

Shield

board

(metal,

L-shaped)

2225021100

Shield

board

(metal,

flat)

2225011200

Shield

sheet

(foiled

paper)

2216031300

Insulation

spacer

(vinyl

chloride)

13439120

Connector

housing

5045-04A

4P

13439123

Connector

housing

5045-07A

7P

13429143

Connector-housing

EMC-S0760

7P

2341017100

Connector

wiring

assy

4P

2341018000

Connector

wiring

assy

7P

2341030700

Connector

wiring

assy

7P

2225021501

Shield

board

(metal,

U-shaped)

13439125

Connector

housing

5045-090A

9A

13429145

Connector

housing

EMCS0960

9P

2341043400

Connector

wiring

assy

9P

2341030300

Connector

wiring

assy

9P

13439514

Connector

PS-30

SD-S4TS1-1

30P

female

13439516

Connector

PS-30

PA-S4T1-A1

30P

male

2215050900

Spacer

13mmL

HEX

threaded

13459123

GND

terminal

12369511

Cord

bushing

BU4801

12369410

Line

cord

strain

relief

1702B

PS

board

LED

board

SW

board

LED

board

(SDE-1000)

(SDE-1000)

(SDE-1000)

(SDE-1000)

(SDE-1000)

(SDE-1000)

(SDE-1000)

(SDE-1000)

(SDE-1000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

(SDE-3000)

SDE-1000/3000

FEB.

5.1984

CIRCUIT

DESCRIPTIONS

General

Description

SDE-1000/3000,

Digital

Delay

Line,

use

RAMs

as

memory

device

in

which

audio

signals

are

stored

by

means

of

PCM

(Pulse

Coded

Modulation)

method.

The

delay

unit

first

samples

the

input

audio

signal

to

have

a

series

of

discrete

values

of

the

signal

amplitude

at

point.

Each

of

sampled

pulses

is

digitalized

and

stored

into

RAM

cells

as

a

binary

coded

data

which,

when

a

specified

time

passed,

is

read,

restored

to

analog

value,

then

injected

into

audio

path

as

a

delayed

signal.

The

process

can

well

be

compared

to

that

of

conventional

tape

echo

machine

as

shown

in

Fig.

1.

RAM

cells

correspond

to

the

tape

and

the

RAM

accessing

to

a

Record/Play

back

head.

In

operation

R/P

head

first

functions

as

a

playback

head

and

will

read

a

group

of

RAM

cells

being

in

touch

with,

then

quickly

changes

to

a

recording

head

to

record

digital

data

being

fed

from

the

A/D

converter

into

the

same

cells.

The

head

steps

to

the

next

cell

group

and

repeats

the

read

and

write

opera

tions,

then

to

the

third,

fourth

and

so

on

continuously

until

the

time

deter

mined

by

DELAY

TIME

button

comes.

When

the

delay

time

has

passed,

the

head

leaves

the

remaining

cells

unused

and

jumps

to

the

first

cell

group

where

it

reads

the

previously

stored

data

and

writes

the

new

data.

The

number

of

cell

groups

the

head

can

see

is

based

on

DELAY

TIME

setting

and

the

travel

ling

speed

of

the

head

slows

down

one-half

when

in

TIME

X2

mode.

In

other

words,

the

length

of

the

tape

varies

with

Delay

Time

and

the

speed

with

Delay

Time

Range

(also

X1—X1.5

setting

and

MOD

rate).

The

following

description

breaks

major

circuits

down

into

Analog

and

Digital,

starting

with

SDE-1000

circuits

most

of

which

are

also

found

in

SDE-3000,

then

goes

through

the

circuits

featuring

SDE-3000.

One

major

difference

be

tween

two

models

are

their

time

delay

ranges:

SDE-3000

four

times

the

SDE-

1000

in

RAM

memory

capacity.

RAM

MEMORY

CELLS

SDE-1000

See

P.

13

for

SDE-3000

Fig.

1

HEAD

AMP

The

Head

Amp

interfaces

the

unit

wih

a

variety

of

input

signals

so

that

the

unit

can

operate

with

adequate

signal

*

noise

and

without

execessive

limiting

across

the

dynamic

range

of

the

signa

Although

this

amp

has

a

gain

range

of

1

to

24,

VR-6

(INPUT

ATT)

attenuass

the

delay

signal

as

it

is

rotated

from

FCW

position

to

CCW.

The

unit's

overll

gain

is

unity

at

FCW.

NOTE:

Minor

modifications

are

madeon

SDE-1000

head

amp

and

associated

circuits

to

provide

more

headroom

without

sacrificing

tonal

quality

and

sound

level.

Refer

to

Engineering

Chage

in

SDE-1000

section

in

this

manual.

FEEDBACK/MIXING

The

delay

signal

is

mixed

again

with aiew

direct

signal

when

0V

is

placed

on

Q51

gate,

and

out

of

the

delay

line

whn

-14V

is

on

the

gate.

PREEMPHASIS

This

stage

boosts

higher

frequency

corents

to

provide

a

good

S/N

ratio.

GAIN:

unity

at

1kHz

and

2.5

at

10kH

INPUT

jack

1

kHz

TP-2

TIME

X2

OFF

TP-2

TIME

X2

ON

0.2

ms/div

LPF-1

An

'Anti-aliasing

filter

including

tw

filters

of

different

cutoff

point.

Only

one

filter

is

connected

to

the

next

stge

at

a

time.

Pressing

TIME

X2

switch

causes

the

Control

Logic

(IC14,

etc to

place

a

ground

to

the

gate

of

027

and

-14V

to

Q28,

limiting

the

filir's

output

bandwidth

within

10Hz-

8kHz.

Disengaging

the

X2

switch

corlucts

Q28

and

cuts

off

Q27,

extending

the

bandwidth

to

17kHz.

Control

Lgic

also

cuts

off

both

FETs

for

7

sec

after

power

is

first

applied

to

the

un;

and

during

HOLD

ON

mode

or

while

Delay

Time

button

is

manuplated.

*

Aliasing

—

The

type

of

distortioi

that

is

found

in

"sampled"

signal

pro

cessing

system

when

the

signal

has

frtjuency

components

which

exceed

half

the

sampling

frequency.

COMPRESSOR

This

stage

logarithmically

reduces

trudynamic

range

of

the

signal

before

it

is

digitalized.

NOTE:

For

detailed

descriptions

olS/H,

A/D,

D/A,

Main

Controller

and

RAM,

see

corresponding

sections

in

S

E-3000

description.

SAMPLE

&

HOLD

ICs

5A

and

5B,

together

with

C13

extract

a

portion

of

the

input

signal

at

SAH

rate.

The

sampled

audio

is

fed

through

Q8

to

pin

2

of

IC2

where

it

is

compared

with

12

step

voltages

on

pin

3

to

have

its

analog

voltage

repre

sented

by

digital

code

through

A/D

conversion.

NOTE:

SAH

rate

is

constant

regardless

of

DELAY

TIME

setting,

but

varies

when

TIME

X2,

DELAY

TIME

X1/X1.5

or

MODULATION

is

enabled.

A/D

CONVERTER

The

A/D

Converter

employed

here

is

of

Successive

Approximation

consisting

of

SAR

(Successive

Approximation

Registers

in

IC12,

Main

Controller),

ICs

3

and 4

which

boost

TTL

compatible

to

12V,

RM-1

ladder

resistor

which

adds

a

corresponding

analog

weight

to

individual

bit,

Q9

and

Q10

follower

and

comparator

IC2.

In

operation,

SAR

first

sets

the

highest

bit

(MSB)

register

to

H

(1)

whose

output

is,

after

given

the

highest

voltage

at

RM-1,

compared

with

sampled

audio

at

IC2

input.

If

MSB

is

larger

than

the

sampled

audio,

it is

reset

to

L(0)

by

a

H

from

IC2

(D

IN).

If

smaller,

kept

set

and

applied

once

more

together

with

the

second

highest

bit

register

output

(H)

that

is

one-half

the

highest

in

voltage.

The

process

repeats

for

MSBs

while

the

combination

of

SAR

outputs

is

approaching

to

the

sampled

audio

level.

During

the

process,

D

IN

is

also

transferred

to

RAMs

IC9-IC11

to record

H

or

L

of

all

the

bits

which,

when

grouped

into

12

bits,

are

the

data

of

the

sampled

portion

of

audio

input

signal.

FEB.

5,1984

SDE-1000/3000

D/A

CONVERTER

When

the

time

determined

by

DELAY

TIME

has

passed,

some

parts

of

A/D

system

serve

as

D/A

converter.

RAM

stored

12-bit

data

is

transferred

in

time

sequence

(3

bits

parallel

x

4

times)

from

each

RAM

OUT

pin

to

IC12

where

they

are

so arranged

that

they

are

fed

simultaneously

via

D11-D10,

ICs

3,4,

RM-1,

Q9

and

Q10

to

S/H

IC5C

and

IC5D.

EXPANDER

One

half

IC15

NE570

exponentially

amplifies

delayed

audio

to

restore

it

to

the

original

dynamic

range.

LPF-2

The

configuration

analogues

to

LPF-1,

providing

19kHz

bandwidth

when

Q48

is

ON,

or

9.5kHz

when

Q49

is

selected

by

TIME

X2

switch.

Being

an

interporating

filter,

it

smoothes

staircase-like

out

of

the

waveform.

As

just

for

LPF-1,

mute

signals

are

applied

from

Control

Logic

IC14.

DE-EMPHASIS

IC29

and

associated

components

reduce

higher

frequency

components

in

the

delay

line

to

compensate

for

preemphasis,

restoring

the

overall

frequency

res

ponse

to

flat.

PHASE

SELECTOR

Q45,

when

conducted,

change

IC28

into

an

inverter,

reversing

the

delay

out

put

phase

with

respect

to

the

direct

signal.

DELAY

PHASE

"OFF"

INPUT

MIXED

OUT

jack

INPUT

MIXED

OUT

jack

DELAY

OUT

(VR4)

at

CENTER

MAIN

CONTROLLER

IC12

63H-101

a

specially

designed

gate

array

for

controlling

digital

delay

system.

It

clocks

most

of

delay

related

sequences

such

as

A/D,

D/A,

S/H,

RAM

accessing,

etc.

in

time

with

clocks

generated

at

the

internal

timing

gene

rator

which

in

turn

is

clocked

on

MSCK

delivered

from

CLOCK

Generator

IC23.

With

TIME X2

button

activated

IC12

has

an

H

on

RNG

1

pin

and

slows

down

all

timing

sequences

by

one-half

except

REFRESH

cycle.

The

clock

fre

quency

can

be

varied

by

the

external

voltages

to

be

applied

on

FC

pin

or

PA

pin.

As

the

name

implies,

IC12

Main

Controller

is

the

heart

of

the

Delay

Line.

All

the

delay

circuits

will

not

work

correctly

should

the

Main

Controller

fail

to

receive

adequate

clocks

from

IC23.

IC12

PIN

DESCRIPTION

SAH

&

RNG

1

SAH

determines

the

rate

of

sampling

being

performed

at

IC5

which

gates

on

a

high

SAH.

When

TIME

X2

is

engaged,

RNG

1

turns

from

L

to

H,

lengthening

SAH

intervals

from

22.9/is

to

45.8/us

DIN

D

IN

accepts

a

series

of

H

or

L

from

the

comparator

IC2,

resetting

register(s)

in

SAR

on

H

to

omit

it

from

the

subsequent

comparisons.

DOUT

These

Hs

and

Ls

on

D

IN

are

also

transferred

to

RAMs

(IC9-IC11)

and

stored

as

a

set

of

12-bit

data

which

represint

the

amplitude

of

a

portion

of

input

signal

(sampled

audio)

being

fed

to

I(2

pin

2.

D0-D11

During

A/D

conversion

cycle

these

pins

represent

comparison

data

from

internal

SAR.

During

D/A

cycle,

sinultaneously

output

12-bit

RAM

stored

data

which

have

been

read

from

eaci

RAM

in

time

sequence

(3-bits

x

4)

and

temporarily

buffered

in

internal

threi

registers.

A0-A7

These

pins

feed

RAMs

with

addresses:

Refresh,

Row

and

Column.

Since

the

number

of

RAM

cells

involved

in

data

storage

is

varied

with

DELAY

TIME

setting,

the

numbers

of

Row

and

Column

addresses

are also

changed

accord

ingly

while

Refresh

addresses

are

issued

for

all

the

RAM

cells.

RS(RAS)

16

Falling

edges

of

RAS

(Row

Address

Strobe)

enable

each

RAM

to

latch

Row

address

(W/R

cycle)

or

Refresh

address

into

its

designated

cells.

CAS1-CAS3

RAMs

IC9—IC11

latch

Column

addresses

on

negative

edges

of

cocurrent

Column

Address

Strobes

(CAS1CAS3)

which

also

serve

as

Chip

select,

and

read

memory

cell

respectively.

The

data

read

are

routed

to

the

RAM

D

OUT

(pin

14)

while

related

CAS

is

low.

DATA

&

SHI

FT

(SIFT)

As

mentioned

in

general

descriptio,

RAM

cells

used

for

sound

memory

<e

varied

with

time

delay.

IC12contds

RAMs

accessing

sequence

in

accod-

ance

with

DELAY

TIME

DA>

received

at

SHIFT

rate.

The

DATAIs

a

serial

stream

of

16

bits

and'vti

change

between:

,

16

bits—,

MSB

LSB

0000

000

at

0ms

setting

am

0011

111

at

maximum

settg

11

(SDE-3000)

The

DATA/SHIFT

are

transmit^

only

after

DELAY

TIME

or

PRESf

button

is

released.

The

DATA

is

accompanied

by

sevel

mute

signals

to

cancel

unwantl

signals.

MUTE

A:

active

low

when

DEL/

TIME

button

is

mai-

plated.

MUTE

B:

active

low

while

PREST

is

pressed.

To

shorten

the

Mute

periods,

TIC

X2,

MOD.,

and

X1.5

are

disabled.

CPU

.

(IC21)

IC17

P20(DATA)

P21

(SHIFT)

P22(X1.5INH)

P23

(MUTE

A)

^

P23

(MUTE

B)

Q2(TIMEX2)

-

Q4

(MOD)

Interruption(s)

for

Switch

scan

and

LED/numerical

displays.

MINIM

L

TIME/MEMORY

DELAY

TIME

DATA

SDE-1000/3000

FEB.

5,1984

MAIN

CONTROLLER

BLOCK

DIAGRAM

IC12

(SDE-1000)/IC31

(SDE-3000)

CO

CO

A

A

CO

CO

CO

CM

CO

If)

00

in

s

CO

in

in

in

CO

in

CM

in

—

o

in

in

5

00

t

A

TIMING

GENERATOR

DIVIDE

BY

216

A

CM

A

g

V

in

u

o

V

CO

(O

00

CO

CO

CO

DATA

SELECTORS

DATA

SELECTORS

***REHASH

COUNTER

ck

PRESETTABLE

ADDRESS

COUNTER

*>ck

ADDRESS

COUNTER

t T T

T

T

T

f T

T T

T T

T

DATA

SELECTORS

SHIFT

REGISTERS

ck

D-FLIP-FLOPS

in

CO

A

5

CO

CO

A

i

RAM

BANK

SELECTOR

SET

CO

O)

A

CO

SEL

DATA

SELECTORS

V

oo

o

q

V

Q

V

o

CM

CM

CM

CO

CM

in

CM

G

V

oo

CM

CM

Q

V

8

CO

CM

CO

FEB.

5.1984

SDE-1000/3000

o

MAIN

CONTROLLER

TIMING

DIAGRAM

IC12

(SDE-1000)/IC31

(SDE-3000)

MSCK

SAH

DIN

D

11

D10

D

9

D

8

D

7

D

6

D

5

D A

D

3

D

2

D

1

D

0

DOUT

A0-A7

R/W

MODEt

RS16-64

J

REFRESH

MODE-i

RS16-64

J

CAS

1

CAS

2

CAS

3

I

I

I

R/W

MODE-i

wr

-I

RAM

1

RAM

2

RAM

3

DB

0

-l

OFFSET

DAT/

DB

1-1

«*»«**

DB

2

RASFORCOMfWCINQRAM

DB

3

CAS FOR

OOMPWCING

RAM

DB

DB

5

DB

6

DB

7

R/W

MODE

RS16-64

REFRESH

MODE

RS16-64

DB

2

SDE-1000/3000

FEB.

5,1984

MSCK,

HDCK

&

CLOCK

GENERATOR

The

frequency

of

Clock Generator

is

as

follows

(approx):

2.7MHz

at

Normal

1.7MHz

at

TIME

X1.5

2.7M-3.3MHZ

at

MOD

max.

1.7M-2MHz

at

TIME

X1.5/M0D

max.

MSCK

-

Clocks

the

internal

Timing

Generator

that

times

the

most

of

digital

circuits.

HDCK

-

The

frequency

of

HDCK

is

MSCK

or

43Hz

at

normal

mode.

Used

by

the

CPU

as

a time

base

for

calibrating

Delay

Time

display.

The

CPU

fails

to

read

switches

and

jacks

if

HDCK

period

is

outside

7m-50ms.

RAM

1-RAM

3

12-bit

data

read

from

three

RAMs

are

fed

through

these

pins

to

internal

three

shift

registers

for

temporary

storage.

All

the

buffered

bits

are

placed

on

D0-D11

at

a

time

to

form

a

12-bit

parallel

data

to

be

applied

to

D/A

con

verter

for

reproducing

a

part

of

delay

signal.

During

HOLD

ON

the

A/D

converter

remains

active

but

cannot

receive

input

signal.

The

comparator

output

is

inhibited

from

being

written

into

RAMs.

CONTROL

SIGNALS

IN

DIFFE

RENT

MODES

RAMs(IC9-IC11)

Record

the

results

of

Successive

Approximation,

from

MSB

(D11)

to

LSB

(DO),

sharing

12

bits

-

4

specific

bits

for

each

as

shown

in

the

table

at

the

beginning

of

General

Description.

CPU

The

CPU

is

provided

with

a

battery

backup

to

retain

switch,

delay

time

and

preset

settings.

TO

-

Decides

the

operation

mode

of

the

CPU:

+5V--

0V--

SDE-1000

-

SDE-3000

T1

—

Receives

Clock

pulses

through

IC12

HDCK

pin.

The

clock

serves

as

a

time

base

to enable

the

CPU

to

calibrate

Delay

Time

Display

and

is

ignored

by

the

CPU

when

Modulation

is

ON

and

MOD

Foot

control

jack

disengaged.

(See

HDCK,

Main

Controller.)

P20

(DATA)

-

Send

memory

access

control

data

after

every

delay

time

P21

(SHIFT)

-

settings

(see

DATA/SHIFT,

Main

Controller).

P23

-

P10

-

P11

P12

-

P13

-

P14

-

P15

P16

P24

P2'7

DB7

DBO

DB3

DB4

-

DB5

NOTE:

Becomes

"L"

for

muting.

(See

timing

chart

in

DATA,

SHIFT,

Main

Controller.)

Read

SW1-SW10

through

the matrix

in

combination

with

P24-

P27

and

DB7.

Input

from

PRESET

SHIFT

jack.

A

rising

edge

of

this

input

steps

PRESET

memory.

MODULATION

FOOT

CONTROL

jack

input.

With

MODULATION

ON

and

this

input

at

low,

CPU

ignores

T1

input.

For

example,

rotation

of

DELAY

TIME

X1-X1.5does

not

change

TIME

display.

HOLD

jack

input.

When

H,

readings

of

TIME

UP

or

DOWN

and

PRESET

memory

are

inhibited.

PLAY

MATE

jack

input.

Active

rising

edge.

Rising

edge

from

this

pin

latches

the

following

logic

codes

made

by

DB0-DB3

into

Analog

Control

IC17.

TIME

X2,

DELAY

PHASE,

MOD

and

FEEDBACK

Output

of

switch

scan

signals

which

are

read

through

P10

and

P11.

Besides

Control

signals

for

IC17,

these

pins

deliver

numerical

data

to

fluorescent

display

via

IC18

7-seg-decoder.

DB6:

Dot

Point

signal.

Send

LED

lighting

signals.

When

P10,

P11,

P12

and

P15

pins

receive

signals

almost

at

the

same

time,

the

CPU

gives

priority

to

the

signal

first

read.

Example:

PRESET

SHIFT

and

Front

Panel

switches

are

disabled

when

PLAY

MATE

has

been

activated.

10