NOVATECH INSTRUMENTS 3 Rev 1.01, 425A Manual
3.0 HARDWARE INSTALLATION
3.1 Power Connection. Figure 1, shows the rear
panel of the 425A. The required power of +5 Volts
DC is applied through a 2.5mm center positive bar-
rel connector.
3.2 The quality of your power supply may affect the
performance of the 425A. The supply should be free
of ripple and noise (typically <50 mV). Even though
extensive filtering is used on the 425A board, a quiet
and well regulated power supply will ensure opti-
mum performance. If power supplies, other than the
Novatech Instruments provided one, are used, please
verify that your system noise requirement is met.
3.3 Internal Clock. If you plan to use the 425A
internal clock, which is the default mode, no setup
action is required. The on-board VCTCXO is multi-
plied in a phase-locked loop (PLL) to generate the
internal master clock for the DDS ASIC.
3.4 External Clock. There are two customer-sup-
plied clock modes. One (external reference select,
“C r”) uses an internal PLL to multiply an external
10.0 MHz reference to provide a 940.0 MHz master
clock. The other mode (external clock select, “C
e”) allows a 250 to 1000 MHz direct input. In this
mode, the PLL is disabled and the customer clock is
directly used as the master clock.
3.5 If you are providing an external clock or exter-
nal reference, apply your signal to the REF IN BNC
connector on the rear panel. Carefully observe the
amplitude requirements for each mode. Note that
phase noise and stability of the 425A are dependent
upon your supplied clock. Send the appropriate
clock select command to enable your input. This
automatically configures the internal clock circuitry
to generate the correct master clock.
3.6 Unless your external clock is an exact binary
multiple, non-fractional frequency steps will not be
possible, and your frequency settings will need to be
scaled. See Section 4.0, Operation, for scaling infor-
mation.
NOTE:
Consult Novatech Instruments if you require locking
to an external 10.00 MHz standard without round-
off.
3.7 Serial Port Interface Installation. The 425A is
controlled by using an asynchronous serial port
(RS232). Direct connections can be made from most
PCs using a 9-pin monitor extension (male to
female) cable or by using a USB to RS232 (DE9)
adapter. The rear panel connector is a 9-pin female.
3.8 If you are using a different computer, terminal
or other control source, please note that the data TO
the 425A is on pin 3; the data FROM the 425A is
on pin 2 and the COMMON return is on pin 5. Set
your host to 19.2 kBaud, 8 bits, 1 stop bit, no
parity and no hardware flow control.
3.9 Signal Outputs. There are three signal outputs
on the 425A: one channel each of Sine, differential
LVDS and LVCMOS. The outputs are provided on
front panel BNC receptacle connectors. Simply con-
nect your application cables to appropriate output.
The LVDS output requires 100 differential termi-
nation at the destination (internal driver:
SN65LVDS100 or equivalent). All the outputs are at
the same frequency, unless the divider (D0 and PR)
commands have been issued. The LVCMOS output
frequency depends upon the divider and prescaler
settings.
3.10 See Figures 3 and 4 for typical termination of
the LVDS and LVCMOS signals.
NOTE:
The LVCMOS signal is disable by default. Use the
“A e” command to enable it.
Figure 1: Rear Panel
