Copyright 2003 Novatech Instruments, Inc.
initialize.
Signal Descriptions (SYNCHRONOUS MODE):
In the synchronous mode, all internal synthesizers are set to the same frequency and programmed
with phase offsets from the reference synthesizer. The reference synthesizer must always be set to 0o
phase using the PFR control line.
The 1450A/02-AH performs a reset sequence whenever the Mode is changed between Synchronous
and Independent. The output will return to the default (all 10.0MHz) following a Mode change.
through
are the 48 binary frequency data bits presented to the internal DDS. The
frequency output will have 1µHz of resolution per LSB. Since there is no error checking of the user’s
input, care must be taken to ensure that the binary value does not select a frequency output greater
than approximately 120MHz. During programming of all phases, these lines must be held constant at
the desired frequency setting.
through
are the 14 binary phase data bits presented to the internal DDS. The phase of the
output will change by N*360o/16384 or N*π/8192 radians, where N is the value of the binary bits.
The reference synthesizer must always be set to N=0.
With a resolution of 14-bits, the phase can be set to within 0.022o. This corresponds to approximately
6ps at 10MHz. Dispersion due to various propagation delays is greater than this and must be taken
into account in the customer application.
, with PB0 through PB13 set to zero phase and FB0 through FB47 set to the desired frequency,
must be pulsed to set the proper reference phase and frequency.
Any
going LOW is used to signal the on-board circuitry to load a new phase (and frequency,
which must be held constant) into the corresponding DDS registers. After all phases are loaded, CFS
(common frequency strobe) is pulled low to set all the outputs simultaneously. In this mode, BUSY is
not asserted until CFS goes active (see below). To program the synchronous mode properly, the
signals FB0-FB47 must be held constant for all PFn. Only the relative phases should be changed.
While each assertion of a PFn line causes a load sequence taking approximately 430ns on each
internal synthesizer, new data can be set up for the next PFn following a Tld period. CFS must not be
asserted until after BUSY returns to an idle state following the last phase setting.
The negative edge of CFS is inverted and presented on the BUSY line and must be asserted
after all synthesizers have been loaded with appropriate phase data. The last BUSY from any PFn
load must be stable low at least 25ns before the negative edge of CFS. The on-board circuitry takes
approximately 170ns to set the new frequency after CFS has pulsed LOW. For each synthesizer to
have the same frequency, FB0-47 must be held constant at the desired frequency during all PFR and
PF0-7 cycles.
is a VHCMOS compatible
with:
