NEC uPD78F4225Y User manual
MOS INTEGRATED CIRCUIT
µ
PD78F4225Y
16/8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The
µ
PD78F4225Y is a product in the
µ
PD784225Y subseries in the 78K/IV series.
The
µ
PD78F4225YhasaflashmemoryintheplaceoftheinternalROMofthe
µ
PD784225Y. Datacanbewritten
toorerasedfromtheflashmemoryofthe
µ
PD78F4225Fwiththemicrocontrollermountedonaprintedwiringboard.
The
µ
PD78F4225Y is based on the
µ
PD78F4225 with an I2C bus control function appended, and is ideal for
applications in audio visual.
The functions are explained in detail in the following user’s manuals. Be sure to read this manual when
designing your system.
µ
PD784225, 784225Y Subseries User’s Manual - Hardware : Planned
78K/IV Series User’s Manual - Instruction : U10905E
FEATURES
•I
2
C bus serial interface supporting multi task
• Pin-compatible with mask ROM model (except VPP pin)
• Flash memory: 128K bytes
• Internal RAM : 4352 bytes
• Same operating voltage as mask ROM model: VDD = 1.8 to 5.5 V
ORDERING INFORMATION
Part Number Package
µ
PD78F4225YGC-8BT 80-pin plastic QFP (14 ×14 mm)
µ
PD78F4225YGK-BE9 80-pin plastic TQFP (fine pitch) (12 ×12 mm)
Document No. U12377EJ1V0PM00 (1st edition)
Date Published May 1997 N
Printed in Japan
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
©
1997
PRELIMINARY PRODUCT INFORMATION
2
µ
PD78F4225Y
78K/IV Series Product Development
PD784026
µ
PD784038Y
µ
PD784038
µ
PD784915
µ
PD784928
µ
PD784928Y
µ
PD784054
µ
PD784216
µ
PD784225
µ
PD784216Y
µ
PD784225Y
µ
PD784046
µ
PD784908
µ
PD78F4943
µ
Enhaced A/D, 16-bit timer,
power management
Enhanced internal memory capacity,
pin-compatible with PD784026
µ
I2C bus compatible model
: Under mass production
: Under development
Multi-master I2C bus
compatible model Multi-master I2C bus
compatible model
100 pins, enhanced I/O
and internal memory capacity80 pins
Enhanced functions of
PD784915
µ
With 10-bit A/D
For CD-ROM,
Flash memory: 56 KB
With software servo control,
analog circuit for VCRs,
enhanced timer
With IEBusTM controller
3
µ
PD78F4225Y
FUNCTIONS
Item Function
Number of basic instructions 113
(mnemonics)
General-purpose register 8 bits ×16 registers ×8 banks, or 16 bits ×8 registers ×8 banks (memory mapping)
Minimum instruction execution • 160 ns/320 ns/640 ns/1280 ns/2560 ns (main system clock: fXX = 12.5 MHz)
time • 61
µ
s (subsystem clock: fXX = 32.768 KHz)
Internal Flash memory 128 KBytes
memory RAM 4352 Bytes
Memory space 1 MB with program and data spaces combined
I/O port Total 67
CMOS Input 8
CMOS I/O 59
Pins with pull-up 57
resistor
LEDs direct 16
drive output
Real-time output port 4 bits ×2, or 8 bits ×1
Timer/counter 16-bit timer/counter : timer register ×1 Pulse output
Capture/compare register ×2 • PWM/PPG output
• Square wave output
• One-shot pulse output
8-bit timer/counter 1 : timer register ×1 Pulse output
Compare register ×1 • PWM output
• Square wave output
8-bit timer/counter 2 : timer register ×1 Pulse output
Compare register ×1 • PWM output
• Square wave output
8-bit timer/counter 5 : timer register ×1
Compare register ×1
8-bit timer/counter 6 : timer register ×1
Compare register ×1
Serial interface UART/IOE (3-wire serial I/O): 2 channels (
on-chip baud rate generator
)
CSI (3-wire serial I/O, I2C bus supporting multi master): 1 channel
A/D converter 8-bit resolution ×8 channels
D/A converter 8-bit resolution ×2 channels
Clock output Selectable from fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXT
Buzzer output Selectable from fXX/210, fXX/211, fXX/212, fXX/213
Watch timer 1 channel
Watchdog timer 1 channel
Standby • HALT/STOP/IDLE mode
• In power-saving mode (with subsystem clock): HALT/IDLE mode
Interrupt Hardware 25 (internal: 18, external: 7)
Software BRK instruction, BRKCS instruction, operand error
Non-maskable Internal: 1, external: 1
Maskable Internal: 17, external: 6
• 4 programmable priority levels
• 3 service modes: vectored interrupt/macro service/context switching
Supply voltage VDD = 1.8 to 5.5 V
Package • 80-pin plastic QFP (14 ×14 mm)
• 80-pin plastic TQFP (fine pitch) (12 ×12 mm)
Note The pins with ancillary functions are included in the I/O pins.
Pins with
ancillary
functionsNote
4
µ
PD78F4225Y
CONTENTS
1. DIFFERENCES AMONG MODELS IN
µ
PD784225Y SUBSERIES............................................. 5
2. PIN CONFIGURATION (Top View)............................................................................................... 6
3. BLOCK DIAGRAM ......................................................................................................................... 8
4. PIN FUNCTION............................................................................................................................... 9
4.1 Port Pins................................................................................................................................................ 9
4.2 Pins Other Than Port Pins .................................................................................................................. 11
4.3 I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins ........... 13
5. INTERNAL MEMORY SIZE SELECT REGISTER (IMS).............................................................. 16
6. FLASH MEMORY PROGRAMMING ............................................................................................. 17
6.1 Selecting Communication Mode ........................................................................................................ 17
6.2 Flash Memory Programming Function ............................................................................................. 18
6.3 Connecting Flashpro II ........................................................................................................................ 18
7. PACKAGE DRAWINGS ................................................................................................................. 20
APPENDIX A. DEVELOPMENT TOOLS............................................................................................. 22
APPENDIX B. RELATED DOCUMENTS ............................................................................................ 24
5
µ
PD78F4225Y
1. DIFFERENCES AMONG MODELS IN
µ
PD784225Y SUBSERIES
The only difference among the
µ
PD784224Y and 784225Y lies in the internal memory capacity.
The
µ
PD78P4225Yisprovidedwitha128-KBflashmemoryinsteadofthemaskROMoftheabovemodels. These
differences are summarized in Table 1-1.
Table 1-1. Differences among Models in
µ
PD784225Y Subseries
Part Number
µ
PD784224Y
µ
PD784225Y
µ
PD78F4225Y
Item
Internal ROM 96 KBytes 128 KBytes 128 KBytes
(mask ROM) (mask ROM) (flash memory)
Internal RAM 3584 Bytes 4352 Bytes
Internal memory size None Provided
switching register (IMS)
VPP pin None Provided
6
µ
PD78F4225Y
2. PIN CONFIGURATION (Top View)
• 80-pin plastic QFP (14 ×14 mm)
µ
PD78F4225YGC-8BT
• 80-pin plastic TQFP (fine pitch) (12 ×12 mm)
µ
PD78F4225YGK-BE9
Notes 1. Directly connect the TEST/VPP pin to VSS0 in normal operation mode.
2. Connect the AVSS pin to VSS0.
Remark When using in applications where noise from inside the microcomputer has to be reduced, it is
recommended to take countermeasures against noise such as supplying power to VDD0 and VDD1
independently, and connecting VSS0 and VSS1 to different ground lines.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
P15/ANI5
P16/ANI6
P17/ANI7
AVSS
P130/ANO0
P131/ANO1
AVREF1
P70/SI2/RxD2
P71/SO2/TxD2
P72/SCK2/ASCK2
P20/SI1/RxD1
P21/SO1/TxD1
P22/SCK1/ASCK1
P23/PCL
P24/BUZ
P25/SI0/SDA0
P26/SO0
P27/SCK0/SCL0
P40/AD0
P41/AD1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RESET
P127/RTP7
P126/RTP6
P125/RTP5
P124/RTP4
P123/RTP3
P122/RTP2
P121/RTP1
P120/RTP0
P37/EXA
P36/TI01
P35/TI00
P34/TI2
P33/TI1
P32/TO2
P31/TO1
P30/TO0
P67/ASTB
P66/WAIT
P65/WR
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
P50/A8
P51/A9
P52/A10
P53/A11
P54/A12
P55/A13
VSS1
P56/A14
P57/A15
P60/A16
P61/A17
P62/A18
P63/A19
P64/RD
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
AVDD
VDD0
XT1
XT2
TEST/VPP
X1
X2
VDD1
VSS0
P05/INTP5
P04/INTP4
P03/INTP3
P02/INTP2/NMI
P01/INTP1
P00/INTP0
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
7
µ
PD78F4225Y
A8-A19 : Address Bus
AD0-AD7 : Address/Data Bus
ANI0-ANI7 : Analog Input
ANO0, ANO1 : Analog Output
ASCK1, ASCK2 : Asynchronous Serial Clock
ASTB : Address Strobe
AVDD : Analog Power Supply
AVREF1 : Analog Reference Voltage
AVSS : Analog Ground
BUZ : Buzzer Clock
EXA : External Access Status Output
INTP0-INTP5 : Interrupt from Peripherals
NMI : Non-maskable Interrupt
P00-P05 : Port0
P10-P17 : Port1
P20-P27 : Port2
P30-P37 : Port3
P40-P47 : Port4
P50-P57 : Port5
P60-P67 : Port6
P70-P72 : Port7
P120-P127 : Port12
P130, P131 : Port13
PCL : Programmable Clock
RD : Read Strobe
RESET : Reset
RTP0-RTP7 : Real-time Output Port
RxD1, RxD2 : Receive Data
SCK0-SCK2 : Serial Clock
SCL0 : Serial Clock
SDA0 : Serial Data
SI0-SI2 : Serial Input
SO0-SO2 : Serial Output
TEST : Test
TI00, TI01, TI1-TI2 : Timer Input
TO0-TO2 : Timer Output
TxD1, TxD2 : Transmit Data
VDD0, VDD1 : Power Supply
VPP : Programming Power Supply
VSS0, VSS1 : Ground
WAIT : Wait
WR : Write Strobe
X1, X2 : Crystal (Main System Clock)
XT1, XT2 : Crystal (Subsystem Clock)
8
µ
PD78F4225Y
3. BLOCK DIAGRAM
INTP2/NMI
INTP0, INTP1,
INTP3-INTP6
PROGRAMMABLE
INTERRUPT
CONTROLLER
REAL-TIME
OUTPUT PORT
TIMER/COUNTER6
(8 BITS)
TIMER/COUNTER5
(8 BITS)
TIMER/COUNTER2
(8 BITS)
TIMER/COUNTER1
(8 BITS)
TIMER/COUNTER
(16 BITS)
WATCH TIMER
WATCHDOG TIMER
TI00
TI01
TO0
TI1
TO1
TI2
TO2
RTP0-RTP7
CLOCK OUTPUT
CONTROL
A/D
CONVERTER
AV
DD
AV
SS
PCL
BUZ
ANI0-ANI7
D/A
CONVERTER
ANO0
AV
SS
AV
REF1
ANO1
78K/IV
CPU CORE
FLASH
MEMORY
RAM
BAUD-RATE
GENERATOR
RxD1/SI1
TxD1/SO1
ASCK1/SCK1
RxD2/SI2
TxD2/SO2
ASCK2/SCK2
SI0/SDA0
SO0
SCK0/SCL0
BUS I/F
UART/IOE1
RD
ASTB
WR
WAIT
AD0-AD7
A8-A15
A16-A19
PORT1 P10-P17
PORT0 P00-P05
PORT2 P20-P27
PORT3 P30-P37
PORT4 P40-P47
PORT5 P50-P57
PORT6 P60-P67
PORT7 P70-P72
PORT12 P120-P127
PORT13 P130,P131
BUZZER OUTPUT
SYSTEM CONTROL
RESET
XT2
X1
XT1
X2
V
SS0
, V
SS1
V
DD0
, V
DD1
TEST/V
PP
CLOCKED
SERIAL
INTERFACE
BAUD-RATE
GENERATOR
UART/IOE2
EXA
9
µ
PD78F4225Y
4. PIN FUNCTION
4.1 Port Pins (1/2)
Pin Name I/O Alternate Function Function
P00 I/O INTP0
P01 INTP1
P02 INTP2/NMI
P03 INTP3
P04 INTP4
P05 INTP5
P10-P17 Input ANI0-ANI7
P20 I/O RxD1/SI1
P21 TxD1/SO1
P22 ASCK1/SCK1
P23 PCL
P24 BUZ
P25 SI0/SDA0
P26 SO0
P27 SCK0/SCL0
P30 I/O TO0
P31 TO1
P32 TO2
P33 TI1
P34 TI2
P35 TI00
P36 TI01
P37 EXA
P40-P47 I/O AD0-AD7 Port 4 (P4):
• 8-bit I/O port
• Can be set in input or output mode bit-wise.
• All pins set in input mode can be connected to internal pull-up
resistors by software.
• Can drive LEDs.
P50-P57 I/O A8-A15 Port 5 (P5):
• 8-bit I/O port
• Can be set in input or output mode bit-wise.
• All pins set in input mode can be connected to internal pull-up
resistors by software.
• Can drive LEDs.
Port 1 (P1):
• 8-bit input port
Port 0 (P0):
• 6-bit I/O port
• Can be set in input or output mode bit-wise.
• Pins set in input mode can be connected to internal pull-up
resistors by software bit-wise.
Port 2 (P2):
• 8-bit I/O port
• Can be set in input or output mode bit-wise.
• Pins set in input mode can be connected to internal pull-up
resistors by software bit-wise.
Port 3 (P3):
• 8-bit I/O port
• Can be set in input or output mode bit-wise.
• Pins set in input mode can be connected to internal pull-up
resistors by software bit-wise.
10
µ
PD78F4225Y
4.1 Port Pins (2/2)
Pin Name I/O Alternate Function Function
P60 I/O A16
P61 A17
P62 A18
P64 RD
P65 WR
P66 WAIT
P67 ASTB
P70 I/O RxD2/SI2
P71 TxD2/SO2
P72 ASCK2/SCK2
P120-P127 I/O RTP0-RTP7 Port 12 (P12):
• 8-bit I/O port
• Can be set in input or output mode bit-wise.
• Pins set in input mode can be connected to internal pull-up resistor
by software bit-wise.
P130, P131 I/O ANO0, ANO1 Port 13 (P13):
• 2-bit I/O port
• Can be set in input or output mode bit-wise.
Port 6 (P6):
• 8-bit I/O port
• Can be set in input or output mode bit-wise.
• All pins set in input mode can be connected to internal pull-up
resistors by software.
Port 7 (P7):
• 3-bit I/O port
• Can be set in input or output mode bit-wise.
• Pins set in input mode can be connected to internal pull-up resistor
by software bit-wise.
This manual suits for next models
2
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