National Instruments NI 5772R User manual

NI-5772

USER MANUAL AND SPECIFICATIONS

NI 5772R

Digitizer Adapter Module

The NI 5772 is a high-speed digitizer adapter module designed to work in conjunction with

your NI FlexRIO™ FPGA module. The NI 5772 features two analog input (AI) channels with

12-bit resolution and sample rates up to 800 MS/s when using both channels or sample rates

up to 1.6 GS/s when using only one channel. The NI 5772R is available in two versions: an

AC-coupled version and a DC-coupled version.

This document contains signal information and lists the specifications of the NI 5772R, which

is composed of the NI FlexRIO FPGA module and the NI 5772. This document also contains

tutorial sections that demonstrate how to acquire data using a LabVIEW FPGA Example VI

and how to create and run your own LabVIEW project with the NI 5772R.

Note NI 5772R refers to the combination of your NI 5772 adapter module and

your NI FlexRIO FPGA module. NI 5772 refers to your NI 5772 adapter module

only.

Note Before configuring your NI 5772R, you must install the appropriate software

and hardware. Refer to the NI FlexRIO FPGA Module Installation Guide and

Specifications for installation instructions.

The following figure shows an example of a properly connected NI FlexRIO device.

Figure 1. NI FlexRIO Device

NI FlexRIO

Adapter Module + = NI FlexRIO Device

NI FlexRIO

FPGA Module

Contents

Electromagnetic Compatibility Guidelines...............................................................................2

Connecting Cables....................................................................................................................3

How to Use Your NI FlexRIO Documentation Set..................................................................3

Front Panel and Connector Pinouts...........................................................................................5

AUX I/O Connector..........................................................................................................7

Block Diagrams.........................................................................................................................8

NI 5772 Component-Level Intellectual Property (CLIP).........................................................9

NI 5772 CLIP..................................................................................................................10

Using Your NI 5772R with a LabVIEW FPGA Example VI.................................................12

FPGA Example VI Steps................................................................................................12

Creating a LabVIEW Project and Running a VI on an FPGA Target............................13

Clocking..................................................................................................................................16

NI 5772 Specifications............................................................................................................18

Analog Input (AI 0 and AI 1)..........................................................................................19

Analog Input Impedance.................................................................................................21

Internal Sample Clock.....................................................................................................27

CLK IN...........................................................................................................................28

REF IN............................................................................................................................28

TRIG (I/O)......................................................................................................................28

AUX I/O (Port 0 DIO <0..3>, Port 1 DIO <0..3>, and PFI <0..3>)...............................29

EEPROM Map................................................................................................................29

Power..............................................................................................................................30

Physical...........................................................................................................................30

Environment....................................................................................................................30

Compliance and Certifications........................................................................................31

Worldwide Support and Services....................................................................................33

Installing PXI EMC Filler Panels...........................................................................................33

Electromagnetic Compatibility Guidelines

This product was tested and complies with the regulatory requirements and limits for

electromagnetic compatibility (EMC) stated in the product specifications. These requirements

and limits are designed to provide reasonable protection against harmful interference when the

product is operated in the intended operational electromagnetic environment.

This product is intended for use in industrial locations. However, harmful interference may

occur in some installations, when the product is connected to a peripheral device or test object,

or if the product is used in residential or commercial areas. To minimize interference with

radio and television reception and prevent unacceptable performance degradation, install and

use this product in strict accordance with the instructions in the product documentation.

Furthermore, any modifications to the product not expressly approved by National Instruments

could void your authority to operate it under your local regulatory rules.

Caution To ensure the specified EMC performance, you must install PXI EMC

Filler Panels (National Instruments part number 778700-01) in adjacent chassis

slots. Installing PXI EMC Filler Panels in all empty slots is recommended. You can

2 | NI 5772R User Manual and Specifications | ni.com

order a kit of six single slot EMC Filler Panels directly from NI by visiting

ni.com/info and entering partnumber.

Caution To ensure the specified EMC performance, operate this product only with

shielded cables and accessories.

Caution To ensure the specified EMC performance, the length of all I/O cables

must be no longer than 3 m (10 ft).

Related Information

Installing PXI EMC Filler Panels on page 33

Connecting Cables

1. Use any shielded 50 Ω SMA cable to connect signals to the connectors on the front panel

of your device.

2. Use the SHH19-H19-AUX cable (NI part number: 152629-01 or 152629-02) to connect

to the digital I/O (DIO) and programmable function interface (PFI) signals on the

AUX I/O connector. NI recommends using the SCB-19 connector block to access the

DIO and PFI signals.

How to Use Your NI FlexRIO

Documentation Set

Refer to Figure 2 and Table 1 to learn how to use your FlexRIO documentation set.

NI 5772R User Manual and Specifications | © National Instruments | 3

Figure 2. How to Use Your NI FlexRIO Documentation Set.

LabVIEW FPGA

Module Help

NI FlexRIO

Help

LabVIEW

Examples

INSTALL Hardware

and Software

CONNECT Signals

and Learn About

Your Adapter

Module

LEARN About

LabVIEW FPGA

Module

PROGRAM Your

NI FlexRIO System

in LabVIEW FPGA

Module

NI FlexRIO FPGA Module

Installation Guide and Specifications

NI FlexRIO Adapter Module

User Guide and Specifications

Are

ou New to

LabVIEW FPGA

Module?

Yes No

Table 1. NI FlexRIO Documentation Locations and Descriptions

Document Location Description

NI FlexRIO FPGA

Module Installation

Guide and Specifications

Available from the Start

menu and at ni.com/

manuals.

Contains installation instructions for

your NI FlexRIO system and

specifications for your FPGA module.

NI 5772R User Manual

and Specifications (this

document)

Available from the Start

menu and at ni.com/

manuals.

Contains signal information,

examples, CLIP details, and

specifications for your adapter

module.

LabVIEW FPGA Module

Help

Embedded in LabVIEW

Help and at ni.com/

manuals.

Contains information about the basic

functionality of the LabVIEW FPGA

Module.

NI FlexRIO Help Available from the Start

menu and at ni.com/

manuals.

Contains FPGA Module, adapter

module, and CLIP configuration

information.

LabVIEW Examples Available in NI Example

Finder.

Contains examples of how to run

FPGA VIs and Host VIs on your

device.

4 | NI 5772R User Manual and Specifications | ni.com

Table 1. NI FlexRIO Documentation Locations and Descriptions (Continued)

Document Location Description

IPNet ni.com/ipnet Contains LabVIEW FPGA functions

and intellectual property to share.

NI FlexRIO product

page

ni.com/flexrio Contains product information and

data sheets for NI FlexRIO devices.

Front Panel and Connector Pinouts

Table 2 shows the front panel connector and signal descriptions for the NI 5772.

Caution To avoid permanent damage to the NI 5772, disconnect all signals

connected to the NI 5772 before powering down the module, and connect signals

only after the adapter module has been powered on by the NI FlexRIO FPGA

module.

NI 5772R User Manual and Specifications | © National Instruments | 5

Table 2. NI 5772 Front Panel Connectors

Device Front Panel Connector Signal Description

CLK IN

REF IN

AI 0

AI 1

TRIG

AUX

I/O

NI 5772

1.6 GS/s

12-Bit

Digitizer

INSTRUMENTS

NATIONAL

REF IN External Reference Clock input, 50 Ω, single-ended.

CLK IN External Sample Clock input, 50 Ω, single-ended.

AI 0 Analog input channel 0, 50 Ω, single-ended.

AI 1 Analog input channel 1, 50 Ω, single-ended.

TRIG Trigger input and output channel.

AUX I/O Refer to Table 3 for the signal list and descriptions.

Caution Connections that exceed any of the maximum ratings of any connector on

the NI 5772R can damage the device and the chassis. NI is not liable for any damage

resulting from such connections.

Related Information

NI 5772 Specifications on page 18

6 | NI 5772R User Manual and Specifications | ni.com

AUX I/O Connector

Table 3. NI 5772 AUX I/O Connector Pin Assignments

AUX I/O Connector Pin Signal Signal Description

1 DIO Port 0 (0) Bidirectional single-ended (SE) digital I/O (DIO)

data channel.

2 GND Ground reference for signals.

3 DIO Port 0 (1) Bidirectional SE DIO data channel.

4 DIO Port 0 (2) Bidirectional SE DIO data channel.

5 GND Ground reference for signals.

6 DIO Port 0 (3) Bidirectional SE DIO data channel.

7 DIO Port 1 (0) Bidirectional SE DIO data channel.

8 GND Ground reference for signals.

9 DIO Port 1 (1) Bidirectional SE DIO data channel.

10 DIO Port 1 (2) Bidirectional SE DIO data channel.

11 GND Ground reference for signals.

12 DIO Port 1 (3) Bidirectional SE DIO data channel.

13 PFI 0 Bidirectional SE DIO data channel.

14 NC No connect.

15 PFI 1 Bidirectional SE DIO data channel.

16 PFI 2 Bidirectional SE DIO data channel.

17 GND Ground reference for signals.

18 +5 V +5 V power (10 mA maximum).

19 PFI 3 Bidirectional SE DIO data channel.

Caution The AUX I/O connector accepts a standard, third-party HDMI cable, but

the AUX I/O port is not an HDMI interface. Do not connect the AUX I/O port on the

NI 5772 to the HDMI port of another device. NI is not liable for any damage

resulting from such signal connections.

NI 5772R User Manual and Specifications | © National Instruments | 7

Block Diagrams

The following figure shows the NI 5772 block diagram and signal flow.

Figure 3. NI 5772 Connector Signals and NI 5772 CLIP Signal Block Diagram

TRIG

NI 5772 Adapter Module

AI 0

AI 1

AUX I/O

Analog

Path

ADC Clock

ADC Data

SClk

I2C (Shared) Example

VI*

Sda

ADC Control

ADC12D800RF

LabVIEW FPGA CLIP

Analog

Path

AD7291

Temperature

Sensor

REF IN

ADC Clock

ADC Data

ADC

Interface

ADC

Interface

AI 0 Data

<N..N-3>

AI 1 Data

<N..N-3>

AI 0 Data Over Range

<N..N-3>

AI 1 Data Over Range

<N..N-3>

Trigger Input (Sync & Async)

Trigger Output

Trigger WE

ADC12D800RF

DIO Port 1 WE Request

DIO Port 1 Rd Data <0...3>

DIO Port 1 Wr Data <0...3>

DIO Port 1 WE Actual

PFI <0...3> WE

PFI <0...3> Rd Data

PFI <0...3> Wr Data

DIO Port 0 WE Request

DIO Port 0 Rd Data <0...3>

DIO Port 0 Wr Data <0...3>

DIO Port 0 WE Actual

CLK IN

Clk Control

PLL Locked

PLL

HMC 703

PLL Loop

Filter

800 MHz

VCO

Enable PLL

Sync Clock

(IoModSyncClk)

User Command Idle

User Data

User Command Status

User Return

User Error

PLL Locked

Initialization Done

SPI Device Select

SPI Write

SPI Write Data

SPI Address

SPI Read Data

SPI Idle

Configuration

Engine

User Command

User Command Commit

SPI Read

Vconstant

(Free-Running)

I2C (Shared)

Related Information

Using Your NI 5772R with a LabVIEW FPGA Example VI on page 12

8 | NI 5772R User Manual and Specifications | ni.com

NI 5772 Component-Level Intellectual Property

(CLIP)

The LabVIEW FPGA Module includes component-level intellectual property (CLIP) for HDL

IP integration. NI FlexRIO devices support two types of CLIP: user-defined and socketed.

•User-defined CLIP allows you to insert HDL IP into an FPGA target, enabling VHDL

code to communicate directly with an FPGA VI.

•Socketed CLIP provides the same IP integration of the user-defined CLIP, but also allows

the CLIP to communicate directly with circuitry external to the FPGA. Adapter module

socketed CLIP allows your IP to communicate directly with both the FPGA VI and the

external adapter module connector interface.

The following figure shows the relationship between an FPGA VI and the CLIP.

Figure 4. CLIP and FPGA VI Relationship

Adapter Module

CLIP Socket

LabVIEW

FPGA VI

User-Defined

CLIP

NI FlexRIO FPGA Module

FPGA

External

I/O Connector

Adapter

Module

Socketed

CLIP

User-Defined

CLIP Fixed I/O

DRAM 0

CLIP Socket

Socketed

CLIP

DRAM 1

CLIP Socket

Socketed

CLIP

Fixed I/O

DRAM 0 DRAM 1

The NI 5772 ships with socketed CLIP items that add module I/O to the LabVIEW project.

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