Kinetic P580 User manual

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Model P580

RelayMultiplexer

User’s Manual



Copyrightby

KineticSystemsCompany,LLC

Lockport,Illinois

Allrightsreserved

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

Revision History

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6/29/04SCKUpdatedthedocumenttoaddtheStepScannerfunctionality.Thisisimplementedasa

write‐onlyregisterlocatedat1Chex.Also,addedtheRevisionhistoryboxfortracking

changes.

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Model P580 Chapter 4: Configuration and Operational Registers

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Chapter 1: Understanding the P580

Overview

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TheP580isadoublewidth3UPXImodulethatfunctionsasamultiplexer.TheP580incorporatestwo

independentdifferentialanalogpathsthatcanbeconnectedtoanyof34differentialsignalpaths

throughthe68positionfrontpanelmountedSCSIconnector.Also,eachpathcanberoutedtoanyof

thefourSMBfrontpanelmountedconnectors.

ThefollowingdiagramshowstheinternalarchitectureoftheP580.



Channel

Instr

‐

Instr

‐

Instr

‐

Instr

‐

Path A

Path B

Relay

n‐

Sca

‐

To Relay

PXITri

er

PXII/O

Model P580 Chapter 4: Configuration and Operational Registers



Basic Circuit Operation

Model P580 Chapter 4: Configuration and Operational Registers

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Front-panel Connector Pinout

Model P580 Chapter 4: Configuration and Operational Registers

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Chapter 2: Configuration and Operational Reg-

isters

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Required Configuration Registers

Operational Registers

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ThefollowingoperationalregistersareusedtoconfiguretheP580.Thefollowingtableshowstheregisters

andtheiroffsetsrelativetotheassignedbaseaddressinmemory.

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Offset Register Access

00h Instrument Connection Register Write/Read

04h Trigger Connection Register Write/Read

08h Path A Connection Register Low Write/Read

0Ch Path A Connection Register High Write/Read

10h Path B Connection Register Low Write/Read

14h Path B Connection Register High Write/Read

18h Scanner Configuration Register Write/Read

1Ch Step Scanner Write-Only

1Ch-FFCh Reserved -

1000h Scanner Memory Location 1 Write/Read

1004h Scanner Memory Location 2 Write/Read

1008h Scanner Memory Location 3 Write/Read

100Ch Scanner Memory Location 4 Write/Read

1FF8h Scanner Memory Location 1023 Write/Read

1FFCh Scanner Memory Location 1024 Write/Read

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Model P580 Chapter 4: Configuration and Operational Registers



Instrument Connection Register 00h

Thisread/writeregisterselectspathtowhichtheexternalinstrumentsareconnectedthroughthefront

panelmountedSMBconnectors.Thisregisterisalsousedtocontrolthegroundingofeachanalogpath.

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Read/write

0 0 0 0 0 0 0 0 0 0 0 0 0 0 GND

PTHB

GND

PTHA

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 INST

SL4B

INST

SL4A

0 0 INST

SL3B

INST

SL3A 0 0

INST

SL2B

INST

SL2A 0 0

INST

SL1B

INST

SL1A

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GND PTHB Bit 17

TheGroundPathBbitisusedtogroundthedifferentialpaironanalogPathB.Boththepositiveand

negativesideofthepatharegrounded.Settingthisbittoa“1”groundsthepathanda“0”removesthe

pathfromground.

GND PTHA Bit 16

TheGroundPathAbitisusedtogroundthedifferentialpaironanalogPathA.Boththepositiveand

negativesideofthepatharegrounded.Settingthisbittoa“1”groundsthepathanda“0”removesthe

pathfromground.

INST SL4B and INST SL4A Bits 13 and 12

TheInstrumentSelect4Band4Abitsareusedtocontroltheconnectionofthefrontpanelmounted

INST4SMB.ThisSMBconnectorcanremainedunconnectedtoanypath,connectedtoPathA,orcon‐

nectedtoPathB.Thebinarycombinationofthesebitsdeterminetheconnectionpathasshowninthe

followingtable.



INSTSL4BINSTSL4AConnection

00NotConnected

01ConnectedtoPathA

10ConnectedtoPathB

11ConnectedtoPathAandPathB

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INST SL3B and INST SL3A Bits 9 and 8

TheInstrumentSelect3Band3Abitsareusedtocontroltheconnectionofthefrontpanelmounted

INST3SMB.ThisSMBconnectorcanremainedunconnectedtoanypath,connectedtoPathA,orcon‐

nectedtoPathB.Thebinarycombinationofthesebitsdeterminetheconnectionpathasshowninthe

followingtable.



INSTSL3BINSTSL3AConnection

00NotConnected

01ConnectedtoPathA

Model P580 Chapter 4: Configuration and Operational Registers



10ConnectedtoPathB

11ConnectedtoPathAandPathB



INST SL2B and INST SL2A Bits 5 and 4

TheInstrumentSelect2Band2Abitsareusedtocontroltheconnectionofthefrontpanelmounted

INST2SMB.ThisSMBconnectorcanremainedunconnectedtoanypath,connectedtoPathA,orcon‐

nectedtoPathB.Thebinarycombinationofthesebitsdeterminetheconnectionpathasshowninthe

followingtable.



INSTSL2BINSTSL2AConnection

00NotConnected

01ConnectedtoPathA

10ConnectedtoPathB

11ConnectedtoPathAandPathB



INST SL1B and INST SL1A Bits 1 and 0

TheInstrumentSelect1Band1Abitsareusedtocontroltheconnectionofthefrontpanelmounted

INST1SMB.ThisSMBconnectorcanremainedunconnectedtoanypath,connectedtoPathA,orcon‐

nectedtoPathB.Thebinarycombinationofthesebitsdeterminetheconnectionpathasshowninthe

followingtable.



INSTSL1BINSTSL1AConnection

00NotConnected

01ConnectedtoPathA

10ConnectedtoPathB

11ConnectedtoPathAandPathB



Trigger Connection Register 04h

Thisread/writeregisterisusedtoconfiguretheconnectionofthePXITriggersignalstoeitherPathAor

B.ThisfeatureisincludedinthismodulesothattestingofotherKSCproductthatusesthePXItrigger

linescanbeaccommodated.Whenconfiguringthetriggerlines,ensurethatthedirectionofthetrigger

signalisobserved.InputandOutputreferencestothetriggerlinesarereferredtotheP580.Inputsare

receivedbytheP580andoutputsaregeneratedbytheP580.

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Read/write

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 TRGB

DIR

TRG

SL4B

TRG

SL3B

TRG

SL2B

TRG

SL1B 0 0 0

TRGA

DIR

TRG

SL4A

TRG

SL3A

TRG

SL2A

TRG

SL1A

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Model P580 Chapter 4: Configuration and Operational Registers



TRGB DIR Bit 12

TheTriggerBDirectionbitisusedtospecifythedirectionofthePXItriggerlineconnectedtoPathB.

Settingthisbittoa“1”specifiesthatthetriggerlineisanoutputfromtheP580anda“0”specifiesthe

triggerlineasaninput.

TRG SL4B through TRG SL1B Bits 11-8

TheTRGSL4BthroughTRGSL1BbitsareusedtoselectthetriggerlinewhichconnectsuptoPathBof

theP580.Thebinarycombinationofthesebitsdeterminetheconnectionpathasshowninthefollowing

table.



TRGSL4B–TRGSL1BValueTriggerConnectedtoPathB

0Disabled

1PXITriggerLine0

2PXITriggerLine1

3PXITriggerLine2

4PXITriggerLine3

5PXITriggerLine4

6PXITriggerLine5

7PXITriggerLine6

8PXITriggerLine7

9PXIStarTrigger

TRGA DIR Bit 4

TheTriggerADirectionbitisusedtospecifythedirectionofthePXItriggerlineconnectedtoPathA.

Settingthisbittoa“1”specifiesthatthetriggerlineisanoutputfromtheP580anda“0”specifiesthe

triggerlineasaninput.

TRG SL4A through TRG SL1A Bits 3-0

TheTRGSL4AthroughTRGSL1AbitsareusedtoselectthetriggerlinewhichconnectsuptoPathAof

theP580.Thebinarycombinationofthesebitsdeterminetheconnectionpathasshowninthefollowing

table.



TRGSL4A–TRGSL1AValueTriggerConnectedtoPathA

0Disabled

1PXITriggerLine0

2PXITriggerLine1

3PXITriggerLine2

4PXITriggerLine3

5PXITriggerLine4

6PXITriggerLine5

7PXITriggerLine6

8PXITriggerLine7

9PXIStarTrigger

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