Intel 82555 User manual

82555 10/100 Mbps LAN Physical Layer

Interface

Networking Silicon

Datasheet

Product Features

■Optimal integration for lower cost solutions

—Integrated 10/100 Mbps single chip

physical layer interface solution

—Complete 10/100 Mbps MII compliance

with MDI support

—Full duplex operation in 10 Mbps and

100 Mbps modes

—IEEE 802.3u Auto-Negotiation support

for 10BASE-T half and full duplex,

100BASE-TX half and full duplex, and

100BASE-T4 configurations

—Parallel detection algorithm for legacy

support of non-Auto-Negotiation

enabled link partner

—Integrated 10BASE-T transceiver with

built in transmit and receive filters

—Glueless interface to T4-PHY for

combination TX/T4 designs with single

magnetics

—Glueless support for 4 LEDs: activity,

link, speed, and duplex

—LED function mapping support via MDI

—Low external component count

—Single 25 MHz clock support for 10

Mbps and 100 Mbps (crystal or

oscillator)

—Single magnetics for 10 Mbps and 100

Mbps operation

—QFP 100-pin package

■Performance enhancements

—Flow control support for IEEE 802.3x

Auto-Negotiation and Bay Technologies

PHY Base* scheme

—Adaptive Channel Equalizer for greater

functionality over varying cable lengths

—High tolerance to extreme noise

conditions

—Very low emissions

—Jabber control circuitry to prevent data

loss in 10 Mbps operation

—Auto-polarity correction for 10BASE-T

—Software compatible with 82557 drivers

■Repeater functionality

—Repeater mode operation

—Support for forced speed of 10 Mbps

and 100 Mbps

—Automatic carrier disconnect for IEEE

802.3u compliance

—Auto-Negotiation enable/disable

capability

—Receive port enable function

—Support for 32 configurable addresses

—Narrow analog side (14 mm) for tight

packing in repeater and switch designs

Document Number: 666252-004

Revision 2.0

March 1998

Notice:

82555 — Networking Silicon

ii Datasheet

Revision History

■Low power consumption

—Typical total solution power including

all resistors and magnetics:

- 275 mA 100BASE-TX

- 230 mA 10BASE-T

- 250 mA Auto-Negotiation

—300 mA maximum total solution power

in DTE (adapter) mode

—Power-down of 10BASE-T/100BASE-

TX sections when not in use

■Added modes for design, testing, and

manufacturability

—Test Access Port (TAP)

- NAND Tree

- Board Level Functional Test (BIST)

—Programmable bypass for 4B/5B

encoding/decoding and scrambler/

descrambler

—Diagnostic loopback mode

Revision

Date Revision Description

Jan. 1997 1.0 First external release of the preliminary datasheet

Apr. 1997 1.1 First release edition

Mar. 1998 2.0 General editing

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 82555 10/100 Mbps LAN Physical Layer Interface may contain design defects or errors known as errata which may cause the product to deviate

from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:

Intel Corporation

P.O. Box 7641

Mt. Prospect IL 60056-7641

or call 1-800-879-4683.

*Third-party brands and names are the property of their respective owners.

Datasheet iii

Networking Silicon — 82555

Contents

1.0 INTRODUCTION..........................................................................................................................1

1.1 Functional Overview........................................................................................................1

1.2 Compliance to Industry Standards ..................................................................................1

2.0 ARCHITECTURAL OVERVIEW...................................................................................................3

2.1 100 Mbps Mode...............................................................................................................3

2.2 10 Mbps Mode.................................................................................................................4

2.3 Media Independent Interface (MII) ..................................................................................5

3.0 PIN DEFINITIONS........................................................................................................................7

3.1 Pin Types .......................................................................................................................8

3.2 Clock Pins ......................................................................................................................8

3.3 Twisted Pair Ethernet (TPE) Pins ...................................................................................8

3.4 Media Independent Interface (MII) Pins .........................................................................8

3.5 Media Access Control/Repeater Interface Control Pins .................................................9

3.6 LED Pins ......................................................................................................................10

3.7 External Bias Pins ........................................................................................................10

3.8 Miscellaneous Control Pins ..........................................................................................11

3.9 Power and Ground Pins ...............................................................................................12

4.0 100BASE-TX ADAPTER MODE OPERATION..........................................................................13

4.1 100BASE-TX Transmit Clock Generation .....................................................................13

4.2 100BASE-TX Transmit Blocks ......................................................................................13

4.2.1 100BASE-TX 4B/5B Encoder ....................................................................13

4.2.2 100BASE-TX Scrambler and MLT-3 Encoder ...........................................14

4.2.3 100BASE-TX Transmit Framing ................................................................15

4.2.4 Transmit Driver ..........................................................................................16

4.3 100BASE-TX Receive Blocks .......................................................................................16

4.3.1 Adaptive Equalizer.....................................................................................17

4.3.2 Receive Clock and Data Recovery ............................................................17

4.3.3 MLT-3 Decoder, Descrambler, and Receive Digital Section......................17

4.3.4 100BASE-TX Receive Framing .................................................................17

4.3.5 100BASE-TX Receive Error Detection and Reporting...............................17

4.4 100BASE-TX Collision Detection ..................................................................................17

4.5 100BASE-TX Link Integrity and Auto-Negotiation Solution...........................................18

4.5.1 Link Integrity...............................................................................................18

4.5.2 Auto-Negotiation ........................................................................................18

4.5.3 Combination Tx/T4 Auto-Negotiation Solution...........................................18

4.6 Auto 10/100 Mbps Speed Selection..............................................................................19

4.7 Adapter Mode Addresses..............................................................................................19

5.0 10BASE-T FUNCTIONALITY IN ADAPTER MODE ..................................................................21

5.1 10BASE-T Transmit Clock Generation..........................................................................21

5.2 10BASE-T Transmit Blocks...........................................................................................21

5.2.1 10BASE-T Manchester Encoder................................................................21

5.2.2 10BASE-T Driver and Filter .......................................................................21

5.3 10BASE-T Receive Blocks............................................................................................21

5.3.1 10BASE-T Manchester Decoder................................................................21

5.3.2 10BASE-T Twisted Pair Ethernet (TPE) Receive Buffer and Filter............21

82555 — Networking Silicon

iv Datasheet

Contents

5.3.3 10BASE-T Error Detection and Reporting.................................................22

5.4 10BASE-T Collision Detection.......................................................................................22

5.5 10BASE-T Link Integrity................................................................................................22

5.6 10BASE-T Jabber Control Function..............................................................................22

5.7 10BASE-T Full Duplex ..................................................................................................23

6.0 REPEATER MODE....................................................................................................................25

6.1 Special Repeater Features............................................................................................25

6.2 Connectivity...................................................................................................................25

7.0 MANAGEMENT DATA INTERFACE..........................................................................................27

7.1 MDI Frame Structure.....................................................................................................27

7.2 MDI Registers................................................................................................................28

7.2.1 MDI Registers 0 - 7....................................................................................28

7.2.2 MDI Registers 8 - 15..................................................................................31

7.2.3 MDI Registers 16 - 31................................................................................31

8.0 AUTO-NEGOTIATION FUNCTIONALITY..................................................................................35

8.1 Description ....................................................................................................................35

8.2 Parallel Detect and Auto-Negotiation............................................................................36

9.0 LED DESCRIPTIONS ................................................................................................................39

10.0 RESET AND MISCELLANEOUS TEST MODES.......................................................................41

10.1 Reset.............................................................................................................................41

10.2 Loopback.......................................................................................................................41

10.3 Scrambler Bypass.........................................................................................................41

10.4 Test Port........................................................................................................................41

11.0 ELECTRICAL SPECIFICATIONS AND TIMING PARAMETERS..............................................43

11.1 Absolute Maximum Ratings ..........................................................................................43

11.2 General Operating Conditions ......................................................................................43

11.3 DC Characteristics ........................................................................................................43

11.3.1 MII DC Characteristics ..............................................................................43

11.3.2 10BASE-T Voltage/Current DC Characteristics ........................................43

11.3.3 100BASE-TX Voltage/Current DC Characteristics ...................................44

11.4 AC Characteristics.........................................................................................................45

11.4.1 MII Clock Specifications.............................................................................45

11.4.2 MII Timing Parameters ..............................................................................46

11.4.3 Repeater Mode Timing Parameters ..........................................................47

11.4.4 Transmit Packet Timing Parameters .........................................................48

11.4.5 Squelch Test Timing Parameters ..............................................................48

11.4.6 Jabber Timing Parameters ........................................................................49

11.4.7 Receive Packet Timing Parameters ..........................................................49

11.4.8 10BASE-T Normal Link Pulse (NLP) Timing Parameters .........................50

11.4.9 Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters ....................50

11.4.10 Reset Timing Parameters .........................................................................51

11.4.11 X1 Clock Specifications ............................................................................51

11.4.12 100BASE-TX Transmitter AC Specification ..............................................52

12.0 82555 PACKAGE INFORMATION.............................................................................................53

Datasheet 1

Networking Silicon — 82555

1.0 Introduction

The 82555 is a highly integrated, physical layer interface solution designed for 10 and 100 Mbps

Ethernet systems based on the IEEE 10BASE-T and 100BASE-TX specifications. 100BASE-TX is

an IEEE 802.3 physical layer specification for use over two pairs of Category 5 unshielded twisted

pair or Type 1 shielded twisted pair cable. 100BASE-TX defines a signaling scheme not only for

100 Mbps, but also provides CSMA/CD compatibility with the 10 Mbps IEEE 802.3 10BASE-T

signaling standard.

1.1 Functional Overview

The 82555 is designed to work in two modes: Data Terminal Equipment (DTE) for adapters and

repeater for hubs and switches. When configured to DTE (adapter) mode, the 82555 incorporates

all active circuitry required to interface 10/100 Mbps Ethernet controllers and CSMA/CD MAC

components to 10 Mbps and 100 Mbps networks. In this and other documents the 82555 may be

referred to as the DTE, Physical Medium Device (PMD), or Physical Layer Medium (PLM). It

supports a direct glueless interface to Intel components such as the 82557 Fast Ethernet controller.

The 82555 also supports the Media Independent Interface (MII) signals as specified in the IEEE

802.3u standard. The figure below shows how the 82555 fits into a 10/100 Mbps Ethernet adapter

design.

When configured to repeater mode, the 82555 incorporates several features that allow it to function

as a Class I or MII level repeater. Section 6.0, “Repeater Mode” on page 25 describes the 82555 in

a repeater type of application.

1.2 Compliance to Industry Standards

When operating in 100 Mbps mode, the 82555 complies with IEEE 802.3u 100BASE-TX

specification. The PMD section with the related changes established in 802.3u 100BASE-TX

complies with ANSI X3.263:1995 TP-PMD, Revision 2.2.

When operating in the 10 Mbps mode, the 82555 complies with the IEEE 802.3 10BASE-T

specification.

Figure 1. 82555 10/100 Mbps Ethernet Solution

Controller/MAC Intel 82555

System Bus Interface

Pair 1

Pair 2

netics

82555 — Networking Silicon

2Datasheet

The 82555 also complies with the IEEE 802.3u Auto-Negotiation and the IEEE 802.3x Full Duplex

Flow Control sections. The MAC interface on the 82555 is a superset of the IEEE 802.3u Media

Independent Interface (MII) standard.

Datasheet 3

Networking Silicon — 82555

2.0 Architectural Overview

The 82555 is an advanced combination of both digital and analog logic which combine to provide a

functional stack between the Media Independent Interface (MII) and the wire through the

magnetics. Figure 2 shows a general block diagram of the 82555 component.

2.1 100 Mbps Mode

In 100BASE-TX mode the 82555 digital subsection performs all signal processing of digital data

obtained from the analog reception and the data to be driven into the analog transmit subsection.

This includes 4B/5B encoding/decoding, scrambling/descrambling, carrier sense, collision

detection, link detection, Auto-Negotiation, data validation, and providing MII to the Media

Access Controller (MAC). The 82555 supports the IEEE defined MII as its MAC interface and

expects the controller to drive the Management Data Input/Output and Management Data Clock

signals to perform the management functions.

In 100BASE-TX mode, the analog subsection of the 82555 performs two functions:

•Transmit: The 82555 converts a digital 125 Mbps stream into MLT-3 format and drives it

through the transmit differential pair onto the physical medium.

Figure 2. 82555 Simplified Block Diagram

82555 — Networking Silicon

4Datasheet

•Receive: The 82555 takes receive analog MLT-3 data from the receive differential pair and

converts it into a digital 125 Mbps stream, recovering both clock and data signals.

2.2 10 Mbps Mode

The 82555 operation in 10BASE-T mode is similar to the 82555 operation in 100BASE-TX mode.

Manchester encoding and decoding is used instead of 4B/5B encoding/decoding and scrambling/

descrambling. In addition, the Transmit Clock and Receive Clock (MII clock signals) provide 2.5

MHz instead of 25 MHz.

Figure 3. 82555 Analog Logic

4b/5b

Encoding

Scrambler

Serialization

MII TX Interface

NRZ to NRZI

NRZI to MLT3

4b/5b

Decoding

De-scrambler

Serial to 5B

MII RX Interface

NRZI to NRZ

MLT3 to NRZI

Magnetics Module

RJ-45 Connector

12345678

Datasheet 5

Networking Silicon — 82555

The 82555 provides a glueless interface to Intel components such as the 82557 Fast Ethernet

Controller, as well as any MII compatible device. Figure 4 shows a schematic-level diagram of the

82557 Fast Ethernet controller implementation connected to the 82555 using the MII interface.

2.3 Media Independent Interface (MII)

The 82555 supports the Media Independent Interface (MII) as its primary interface to the MAC.

The MII Interface is summarized in Table 1.

Figure 4. Intel 82557/82555 Solution

82557

Flash

(optional)

EEPROM

(

optional

)

PCI Bus Si

nals

82555

RXD[3:0]

RXC

RXERR

RXDV

CRS

COL

TXD[3:0]

TXC

TXEN

MDC

MDIO

RESET

Table 1. 82555 MII

Signal

Name Description Direction Clock

Reference MII Signal Supported

by the 82555?

TXC Transmit Clock From 82555

(adapter mode only) -- Yes

TXD[3:0] Transmit Data From MAC TXC Yes

TXEN Transmit Enable From MAC TXC Yes

COL Collision Detect From 82555 Asynchronous Yes

CRS Carrier Sense From 82555 Asynchronous Yes

RXC Receive Clock From 82555 -- Yes

RXD[3:0] Receive Data From 82555 RXC Yes

RXDV Receive Data Valid From 82555 RXC Yes

RXERR Receive Error From 82555 RXC Yes

MDC Management Data

Clock From manager -- Yes

MDIO Management Data

Input/Output From manager MDC Yes

82555 — Networking Silicon

6Datasheet

TXERR Transmit Error

(repeater mode only) From RIC TXC Yes

Table 1. 82555 MII

Signal

Name Description Direction Clock

Reference MII Signal Supported

by the 82555?

Table of contents

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