HP 13220 Manual

P

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Mod u1e

Manual

Part

No.

13220-91087

REVISED

JAN···

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4····B2

DATA

TERMINAL

TECHNICAL

INFORMATION

HEWLETT~PACKARD

Printed

in

U.S.A.

P

f'

0 c

(~~:;

~:;

0 7' M

()

d u1e

Manual

Part

No.

13220-91087

I~EVISED

JAN···

()

4····0t?

NOTICE

The

inforMation

contained

in

this

dOCUMent

is

subject

to

change

w:i.ti"lou"t

notic€~.

HEWl..ETT····Pt-.CI{ARD t'\AI{EB

NO

WARI~ANTY

OF ANY

I{IND

WITH

'~EGAI~l)

TO

THIS

MATERIAL,

INCLUDING,

BUT

NOT

LIMITED

TO

THE

IMPLIED

WARRANTIES

OF

MERCHANTABILITY

AND FITNESS

FOR

A

PARTICULAR

PURPOSE.

Hewlett-Packard

shall

not

be

liable

for

errors

contained

herein

or

for

incidental

or

con~)f:~quf.·!n·t:i.al

dat

...

aqE~s

in

c()nn~:~ction

with

th(·!

fUl'nis;hinq,

~)E~l'for'Manc:~?,

or

use

of

this

Material.

This

dOCUMent

contains

proprietary

inforMation

which

is

protected

by

cop

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by

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NOTE:

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DATA

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(HP j.3

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) .

i.O

IN"l"RODUCTION

The

02620-60087

Processor

PCA

perforMs

the

terMinal

logic

functions

for

the

2622A

terMinal.

Its

operation

is

based

on

the

Z80A

Microprocessor

and

the

National

SeMiconductor

8367

CRT

Controller

(CRTC).

The

control

and

I/O

section

of

the

Processor

PCA

provides

control

~;>

i qna1

~:>

,

:i.

n

put

/ 0 ut

put

and

d

i~

tap

roc

(~s~:;:i.

n(J

fun

c t j. 0

n~:;

.

The

MeM

0 r' y

section

provides

16K

bytes

of

dynaMic

RAM

for

display

MeMory,

scratch

pad

MeMory

and

data

buffers,

and

space

for

up

to

six

4K

or

8K

byte

RUMs

of

which

32K

are

used

for

COMplete

terMinal

operation

(8K

of

ROM

optional

with

integral

printer).

The

video

control

section

provides

all

tiMing

signals

for

driving

the

sweep

circuitry

and

video

logic

as

well

as

perforMing

direct

MeMory

access

CDMA)

of

display

data.

A

detailed

description

of

the

operation

of

each

of

these

sections

follows

:i.

n

~:;ec

t

ion

3.

0 .

2.0

OPERATING

PARAMETERS.

A

SUMMary

of

operating

paraMeters

for

the

Processor

Module

is

contained

in

tables

1.0

through

4.0

Table

1.0

Physical

ParaMeters

===============================================================================

Par'

t Si ze (I... x W x

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1

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1

1=============1==============================1=======================1========1

1 I 1 1 1

1 1 1 1 1

1

02620-60087

1

Processor

PCA

1

12.3

x

10.9

x

O.S

1

1.4

1

1 1 1 1

I 1 1 1

1 1 1 1

===============================================================================

1

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Table

2.0

Reliability

and

EnvironMental

InforMation

1

~5220

....

f/1

0

H'7

/

()

~5

Rev JAN-()4····f32

================:========~======================================================

I

EnvironMental:

HP

Class

B

I

Restrictions:

Type

tested

at

product

level

I

I==~===========~==============================================================

I

Failure

Rate:

3.71

(percent

per

1000

hours)

I

===================~======~====================================================

Table

3.0

Power

Supply

RequireMents

-

Measured

(At

+/-5%

Unless

Otherwise

Specified)

===~=============================~=============================================

I

+16

Volt

Supply

+12

Volt

Supply

+5

Volt

Supply

I

-12

Volt

Supply

I

ill 0

MA

@

200

MA

@

2.0

A I @

SO

MA

I

NOT

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:::::::::::

:::: ::::

=

::::

=

::::

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I I I

I

115

volts

ac

I

220

volts

ae

I

I I I

I

~

A I

@.

A I

I I I

I

NOT

APPL.ICABL.E I

NOT

APPLICABLE I

===============================================================================

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DATA 2

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DATA

6

DATA

7

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GND

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GND

Signal

I

Description

I

=============================================\

**

PRINTER

**

Negative

True,

Printer

Strobe

Negative

True,Power

On/Failing

Negative

True,

Write

signal

Negative

True,

Fun~tion

select

bit

1

LSB

-

Negative

True,

Data

MSB

-

Negative

True,

Data

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printer

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Negative

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Printer

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select

bit

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13220-91.08'7/0S

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Table

4.0

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InforMation

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Signal

I

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I

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Negative

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\

-8

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-12V

Power

I

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BATTERY

Positive

Battery

TerMinal

I

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1

BATRET

I

Negative

Battery

TerMinal

I

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'I

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KEY:~

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KEYS

KEY6

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**

SWEEP

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Negative

true,

Half

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Video

N/C

Return

for

half

bright

twisted

pair

Negative

true,

Full

Bright

Video

Return

for

Video

twisted

pair

Return

for

Drive

signals

Negative

True,

Vertical

Drive

Horizontal

Drive

**

KEYBOARD

**

Key

Data

(LSB)

KE~y

Data

Key

Data

Key

Data

Key

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K(~~y

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of

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Pow(~r

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+5v

Power

================================~===============================================

j.

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0

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Module

Table

4.0

Connector

InforMation

(Cont'd)

1

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Rev

JAN-()4'-B2

~===============================================================================

Connector

Signal

and

No. I

NaM€~

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Des;cr'iption

==============1================1==============================================

JS

**

DATA

COMM

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the

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================================================================================

1

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1:3220·-91.

OB'7

10'7

Rev

JAN····

04'-(32

3.0

FUNCTIONAL

DESCRIPTION

Refer

t()

bl()ck

diagraM

(fig.

1),

scheMatic

diagraMs

(figs.

2,3),

tiMing

diagraMs

(figs.

4-8),

COMponent

location

diagraM

(fig.

9)

and

parts

list

(fig.

10)

located

in

the

appendix.

The

following

describes

the

()peration

of

the

three

Major

sections

of

the

Processor

peA)

control

and

lID,

MeMory,

and

video

c()ntrol.

CONTROL.

AND

I/O

SECTION

Clock

A

25.7715

MHz

crystal

is

attached

to

the

CRTC

which

oscillates

at

the

video

d()t

frequency.

This

is

buffered

by

the

CRTC

and

again

by

a

74LS244

(US11)

to

beCOMe

DRCX,

buffered

dot

rate

clock.

This

clock

is

then

divided

by

seven

by

the

748163

(Ub11)

to

produce

3.6816

MHz,

which

is

shaped

by

Q4

and

its

associated

circuitry

to

produce

a

SYMMetrical

clock

for

the

ZaOA,

which

has

a

zero

level

<

0.4SV

and

a

one

level>

4.4V.

This

clock

is

also

divided

by

two

to

produce

a

1.8408

MHz

clock

which

the

datacoMM

chip

(U613)

uses

to

produce

baud

rates.

lOOA

The

laOA

Microprocessor

perforMS

the

Major

control

and

data

Manipula-

tion

functions

of

the

processor

peA.

It

provides

addresses

and

control

signals

to

read

and

write

data

frOM

and

to

both

MeMory

and

I/O

ports.

It

also

responds

to

two

externally

generated

interrupts,

NNMI

and

NINT,

which,

when

enabled,

interrupt

current

execution

and

cause

the

ZaOA

to

branch

to

its

interrupt

service

routine.

The

ZBOA

also

responds

to

a

bus

request

signal,

NBUSREQ,

allowing

the

CRTC

control

of

the

systeM

b u

~:)es

.

At

power

up

(or

reset)

the

ZaOA

begins

executing

instructions

frOM

prograM

MeMory

beginning

at

address

OOOOH.

A

routine

is

executed

which

initializes

variables

and

devices

according

to

inforMation

contained

in

non-volatile

MeM()ry

(CMOS)

and

perforMS

a

self

test

of

ROM

and

RAM.

If

an

error

is

detected

a

series

of

beeps

are

issued

to

the

keyboard

which

indicate

the

failing

ROM

or

RAM.

After

inintialization

the

prograM

enters

a

Major

10()P

responding

to

inputs

frOM

the

keyboard

and

datacoMM

por'ts.

Three

74LS244's

(U4'7,U57,U511)

buffer

the

address

and

control

lines

frOM

the

Z80A.

The

1

of

a

decoder,

U76,

is

used

to

separate

prograM

MeMory

into

six

blocks,

each

BK

bytes

long.

The

addressed

ROM

is

en-

abled

during

a MeMory

read

by

the

TNRD

and

TNMREQ

signals

()r

during

an

instructi()n

fetch

by

the

NMl

signal.

Since

the

tiMe

to

read

the

data

in

an

instruction

fetch

is

less

than

that

for

a

MeM()ry

read,

the

NM1

signal

was

used

to

provide

an

early

enable

of

the

ROM

allowing

it

to

respond

within

the

required

tiMe.

ROMs

with

access

tiMes

of

350

ns

frOM

address

or

300

ns

frOM

enable

are

required

t()

run

the

systeM

at

full

speed.

[PROMs

or

ROMs

with

450

ns

access

tiMes

frOM

address

May

be

used

by

installing

JUMper

WS

and

reMoving

JUMper

W6,

which

causes

the

ZaOA

to

wait

one

cycle

l()nger

during

instructi()n

fetches.

The

quad

latch

U610

and

ass()ciated

gating

provides

the

required

wait

signal

to

th~:~

ZBOA.,

13220

Processor

Module

13220-91087/08

Rev

JAN-04-82

3.1.3

I/O

Ports

CMUS

The

Z80A

is

capable

of

addressing

2S6

different

input/output

ports.

I/O

addresses

froM

the

ZaOA

appear

on

address

bits

AO-A7

and

the

accuMulator

contents

appear

on

bits

A8-A1S.

I/O

addresses

0-7FH

are

used

to

access

locations

in

the

nonvolatile

CMOS

RAM,

U73,

where

configuration

data

is

stored.

Since

the

CMOS

RAM

is

not

fast

enough

to

respond

within

the

I/O

cycle

tiMe

a

wait

state

is

generated

(by

U6l0)

each

tiMe

the

CMOS

RAM

is

accessed.

Diodes

CR6-CR8

ensure

that

around

S

volts

is

always

on

t~e

CMOS

supply

pin.

EMMitter

follower

Circuit,

Q3,

Makes

sure

that

during

a

power

off

the

CMOS

is

always

disabled

before

the

l80A

buses

beCOMe

undefined

and

reMains

so

until

buses

beCOMe

defined

at

power

on.

During

power

off

the

battery

Maintains

CMOS

contents.

If

power

on

configuration

is

to

be

fixed,

the

COMS

RAM

May

be

replaced

by

an

HM7611

PROM

(however

it

Must

be

realized

that

the

standard

read/COMpleMent/write

test

for

the

CMOS

self

test

would

show

a

CMOS

error

since

the

prOM

cannot

be

written).

DATACOMM

The

SY6SS1

Asynchronous

COMMunications

Interface

Adapter

perforMS

the

parallel

to

serial

conversion,

error

detection

and

baud

rate

generation

functions

required

for

serial

data

COMMunication.

It

appears

to

the

laOA

as

four

read

only

and

four

write

only

ports

with

address

bit

TA2

selecting

the

read/write

function.

This

is

done

to

COMpensate

for

the

unique

tiMing

of

the

6500

series

devices.

The

SY6551

is

selected

by

the

rising

edge

of

SELDC

which

is

inverted

frOM

U24,

the

1

of

8

decoder.

The

addresses

of

the

SY6SS1

(U613)

are

AO-A7H.

The

status

inputs

of

the

SY6SSl

produce

undesirable

results

and

therefore

are

forced

to

their

active

low

states

while

the

necessary

status

signals

are

routed

through

another

port.

RS-232

line

driver,

USi4,

and

receiver,

U614,

are

~sed

to

convert

frOM

TTL

levels

to

RS-232

levels

(+-12V)

and

vice

versa.

TranSMitted

signals

are:

send

data

(SD),

terMinal

ready

(TR),

request

to

send

(RS)

and

optional

control

driver

1 (OCD1).

Received

signals

are:

receive

d~ta

(RD),

data

Mode

(DM),

optional

control

receiver

1

(OCR1),

and

clea~

to

send

(eS).

The

datacoMM

subsysteM

operates

in

an

asynChronous,

full-duplex,

point-

to-point

environMent.

Characters

May

be

tranSMitted

and

received

siMultaneously

(full-duplex)

with

character

flow

occurring

over

randOM

tiMe

intervals

(asynchronous).

To

achieve

hardware

synchronization

each

character

is

fraMed

by a

start

bit

and

a

stop

bit

(2

stop

bits

at

110

baud).

The

addition

of

the

fraMing

bits

for

tranSMitted

characters

and

the

detection

of

fraMing

bits

for

the

received

characters

are

done

by

the

SY65S1.

The

parity

(for

error

detection)

of

the

character

is

selectable

(in

the

datacoMM

configuration

Menu)

and

is

also

generated

and

detected

by

the

SY6SS1

which

reports

errors

(parity,

fraMing,

and

overrun)

to

the

ZaOA

by

Means

of

a

status

register

in

the

SY6SS1

which

is

read

when a

character

is

received.

The

data

tranSMission

and

reception

rates

are

set

by

the

ZaOA

in

an

internal

reqister

within

the

SY6SS1.

13220

Processor

Module

13220-91087/09

Rev

JAN-04-82

Rates

are

selectable

(in

the

datacoMM

configuration

Menu) frOM

110

to

9600

baud.

The

datacoMM

status

inputs

and

outputs

provide

the

necessary

control

lines

to

connect

the

terMinal

to

a

host

COMputer

via

a ModeM,

or

to

provide

direct

hardware

handshaking

between

the

terMinal

and

host.

At

power-on

the

TR

and

RS

lines

are

activated

to

indicate

that

the

terMinal

is

ready.

Upon

receipt

of

a

ModeM

disconnect

escape

sequence

(esc

f)

the

TR

line

is

brought

inactive

for

.about

two

seconds

to

disconnect

the

ModeM.

The

presence

of

a

ModeM

connection

is

detected

by

DM

which

causes

the

indicator

"LED"

(an

asterisk

'*')

to

be

displayed

on

the

bOttoM

center

of

the

display.

The

CS

signal

frOM

the

host

when

active

allows

the

terMinal

to

tranSMit

data

and

goes

inactive

to

halt

tranSMission

(the

terMinal

May

ignore

CS

depending

on

datacoMM

configuration).

The

state

of

OCDl

is

controlled

by

a

configuration

strap

with

its

default

state

being

low

(inactive).

This

line

selects

the

ModeM

rate

for

dual

speed

ModeMS. OCRl

is

Monitored

in

datacoMM

self

test

to

detect

the

presence

of

the

loopback

test

hood.

All

ModeM

status

lines

are

active

high

(+12V).

Upon

receipt

of

a

character

frOM

datacoMM

the

SY6SS1

generates

an

interrupt

signal

(NINT)

to

the

lBOA.

This

causes

the

ZaOA

to

branch

to

the

datacoMM

interrupt

service

routine

which

reads

the

SY6S51

status,

clearing

the

interrupt,

and

if

no

errors

are

present,

inputs

th~

character

and

places

it

into

the

datacoMM

buffer

in

RAM.

Characters

for

which

errors

(parity,

fraMing

or

overrun)

are

present

cause

a

delete

character

to

be

placed

in

the

buffer.

Teus

PORTS

The

reMaining

I/O

ports

are

buffered

to

the

ZaOA

data

bus

by

the

biderectional

bus

driver,

U37.

This

was

done

because

of

data

bus

loading.

The

signal

TNRD

selects

the

direction

of

the

driver

which

is

enabled

for

all

I/O

accesses

except

CMOS

RAM

and

datacOMM.

U25

forMS

the

keystatus

port

located

at

address

80H.

The

keystatus

port

returns

the

status

of

8

keys

at

a

tiMe,

which

keys

are

deterMined

by

th~

keyboard/display

port

(U26).

Four

bits

of

the

key

address

(colUMn

address)

are

supplied

by U26

(located

at

address

B8H)

and

three

More

frOM

the

eRTC

scan

line

outputs

(row

address).

As

the

row

address

(scan

line

count)

frOM

the

CRTC

change,

keystates

are

clocked

into

the

keystatus

shift

register

(a

high

bit

indicating

key

active)

frOM

which

they

are

later

read.

The

colUMn

address

is

increMented

(during

an NMI)

for

each

of

the

first

sixteen

display

rows

thereby

scanning

the

entire

range

of

keyboard

addresses.

HP 13220 Manual

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