Freescale Semiconductor C29x User manual
C29x PCIe Card User Guide
Document Number: C29xPCIeUG
Rev 0, 10/2013
C29x PCIe Card User Guide, Rev. 0, 10/2013
2 Freescale Semiconductor, Inc.
Contents
Section number Title Page
Chapter 1
Introduction
1.1 Acronyms..........................................................................................................................................................................7
1.2 Related Documentation.....................................................................................................................................................7
1.3 Architectural Overview.....................................................................................................................................................8
1.4 Board Drawing and Top View..........................................................................................................................................10
Chapter 2
PCIe Use Cases
2.1 PCIe Endpoint Mode.........................................................................................................................................................13
2.2 Standalone Host Mode......................................................................................................................................................14
2.3 PKCAL/SKMM Mode......................................................................................................................................................16
2.4 Secure Boot Mode.............................................................................................................................................................16
Chapter 3
Clocks, Resets, and Power Control
3.1 Clocks...............................................................................................................................................................................19
3.2 Resets................................................................................................................................................................................20
3.3 Power Block Diagram.......................................................................................................................................................21
Chapter 4
On-Board Resources
4.1 DDR Memories.................................................................................................................................................................23
4.2 IFC....................................................................................................................................................................................24
4.2.1 NOR Flash Memory.............................................................................................................................................24
4.2.2 NAND Flash Memory..........................................................................................................................................25
4.3 SerDes...............................................................................................................................................................................26
4.4 Ethernet.............................................................................................................................................................................27
4.4.1 eTSEC1................................................................................................................................................................27
4.4.2 eTSEC2................................................................................................................................................................27
4.5 eSPI...................................................................................................................................................................................28
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Section number Title Page
4.6 RS-232..............................................................................................................................................................................28
Chapter 5
Board Connectors, LED, and Push Button
5.1 Connectors........................................................................................................................................................................31
5.2 Headers.............................................................................................................................................................................31
5.3 Jumpers.............................................................................................................................................................................31
5.4 JTAG/COP Connector......................................................................................................................................................32
5.5 LED...................................................................................................................................................................................33
5.6 Push Button.......................................................................................................................................................................34
Chapter 6
POR Configuration
6.1 POR Settings in Different Boot Location Modes.............................................................................................................40
6.1.1 NOR Flash POR Settings.....................................................................................................................................40
6.1.2 NAND Flash POR Settings..................................................................................................................................41
6.1.3 SPI Flash POR Settings........................................................................................................................................42
Chapter 7
CPLD Specification
7.1 Key Features.....................................................................................................................................................................43
7.2 CPLD Memory Map/Register Definition.........................................................................................................................43
7.2.1 Chip ID1 Register (CPLD_CHIPID1).................................................................................................................44
7.2.2 Chip ID2 Register (CPLD_CHIPID2).................................................................................................................45
7.2.3 Hardware Version Register (CPLD_HWVER)...................................................................................................45
7.2.4 Software Version Register (CPLD_SWVER).....................................................................................................46
7.2.5 Reset Control Register (CPLD_RSTCON)..........................................................................................................46
7.2.6 Flash Control and Status Register (CPLD_FLHCSR).........................................................................................47
7.2.7 Watchdog Control and Status Register (CPLD_WDCSR)..................................................................................48
7.2.8 Watchdog Kick Register (CPLD_WDKICK)......................................................................................................48
7.2.9 Fan Control and Status Register (CPLD_FANCSR)...........................................................................................49
7.2.10 Panel LED Control and Status Register (CPLD_LEDCSR)................................................................................49
7.2.11 Miscellanies Control and Status Register (CPLD_MISCCSR)...........................................................................50
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Section number Title Page
7.2.12 Boot Configuration Override Register (CPLD_BOOTOR).................................................................................50
7.2.13 Boot Configuration Register 1 (CPLD_BOOTCFG1).........................................................................................51
7.2.14 Boot Configuration Register 2 (CPLD_BOOTCFG2).........................................................................................51
7.2.15 Boot Configuration Register 3 (CPLD_BOOTCFG3).........................................................................................52
7.2.16 Boot Configuration Register 4 (CPLD_BOOTCFG4).........................................................................................53
Chapter 8
Programming U-Boot
8.1 Programming U-Boot on a Board having no U-Boot Installed........................................................................................55
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Chapter 1
Introduction
The C29x PCIe is a PCIe card with a Freescale C29x crypto coprocessor system-on-chip
(SoC)/processor.
1.1 Acronyms
The table below lists and explains the acronyms used in this document.
Table 1-1. Acronyms
Term Description
COP Common On-Chip Processor
CTS Clear-To-Send
DIP Dual In-Line Package
ECC Elliptic Curve Cryptography
EP Endpoint
eTSEC Enhanced Three-Speed Ethernet Controller
I2C Inter-Integrated Circuit
IFC Integrated Flash Controller
POR Power-On-Reset
RC Root Complex
RGMII Reduced Gigabit Media Independent Interface
RMII Reduced Media Independent Interface
RTS Ready-To-Send
SerDes Serializer/Deserializer
SoC System-On-Chip
SPI Serial Peripheral Interface
UART Universal Asynchronous Receiver/Transmitter
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1.2 Related Documentation
The table below lists and explains the additional documents that you can refer to, for
more information about C29x PCIe.
Table 1-2. Related documentation
Document Description
C29x Crypto Coprocessor Family
Reference Manual
Defines the functionality of the Freescale C29x family. Freescale C29x family consists
of three highly integrated security processors, optimized for public key acceleration and
secure key management. Each family member combines a Power Architecture
processor core with a high performance security engine, network and high-speed serial
interfaces, DDR and non-volatile memory controllers.
C29x Crypto Offload User Guide Explains the procedure to build, configure, and use different software components for
the Freescale C29x crypto coprocessor device.
C29x PCIe Card Getting Started
Guide
Explains C29x PCIe board settings and physical connections needed to boot the board.
Freescale C29x Crypto Coprocessor
Family Product Brief
Provides an overview of the Freescale C29x family of crypto coprocessor features, and
examples of C29x usage.
1.3 Architectural Overview
The figure below shows the block diagram of C29x.
Architectural Overview
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C29x
Security Fuse Processor
Security Monitor
IFC
Power Management
eSDHC
2x DUART
2x I2C
eSPI, GPIO
Power Architecture
e500-v2 Core
TM
32 KB
D-Cache
32 KB
I-Cache
512 KB
Platform Cache
32-bit
DDR3/3L
Memory
Controller
SEC1
SEC2
SEC3
Coherent System Bus
512 KB
Platfrom
SRAM
eTSEC
eTSEC
4-lane 5 GHz SerDes
PCle
DMA Real Time Debug
JTAG
Figure 1-1. C29x block diagram
The figure below shows the block diagram of the C29x PCIe card.
Magnetics
Magnetics
RS232
RJ45
(Console) RJ45 x2 (Ethernet)
MDI
RS232
XCVR
UART
GE PHY
VSC8641
MDIO
RGMII
DUART
RGMII
C29x
IFC
I2C
SerDes
JTAG SPI
COP
Connector
PCle x4
EEPROM
S25FL 128
SPI IF
I2C IF
Thermal
Monitor
EEPROM
AT24C1024 CORE POWER
12V
PCle Finger
Power
Select
Circuit
12V
Power Jack
Super
Sequencer
Power
Regulators
1.0V
Configs
CPLD
NAND Flash
(4 GB)
NOR Flash
(64 MB)
DDR3
(512 MB)
32-bit
Reset Watch Dog
GE PHY
VSC8641
MDI
Resets
12V
1.5V
GVDD
VTT
3.3V
2.5V
16-bit 8-bit 8-bit
LFC_Data(15:0)/Add(27:0)
TSEC1
DDR
TSEC2
Figure 1-2. C29x PCIe card block diagram
Chapter 1 Introduction
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The C29x PCIe card provides the following integrated functions:
• External interfaces
• One X4 PCIe Gen1 interface
• Two 1 Gb RGMII Ethernet ports
• One RJ45 serial console port that supports one UART up to 115200 bps for
console display
• One JTAG debug interface
• On-board memories
• 64 MB 16-bit NOR flash memory of S29GL512P11TFI0
• 4 GB 8-bit NAND flash memory of K9GBG08U0A
• 512 MB 32-bit DDR3 memory of MT41J128M16
• 16 Mb SPI EEPROM of S25FL128
• Power supplies
• External 12V DC power input
• 2x3 6-pin power connector for ATX power supply
• Headers
• Connector for ADM1069 (power-on control chipset) programming
• Connector for CPLD programming
• Connector for ZL6105 (digital power) programming
• POR configuration
• Supports critical POR settings through DIP switches available on the board
1.4 Board Drawing and Top View
The figure below shows C29x PCIe top side reference drawing.
Board Drawing and Top View
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