Denon AVR-550SD User manual

SERVICE MANUAL

AV SURROUND RECEIVER

MODEL AVR-550SD

TOKYO , JAPAN

S-1147V.01 DE/CDM 0407

Some illustrations using in this service manual are

slightly different from the actual set.

●

Please use this service manual with referring to the

operating instructions without fail.

●

For purposes of improvement, specifications and

design are subject to change without notice.

●

本文中に使用しているイラストは、説明の都合上現物

と多少異なる場合があります。

●

修理の際は、必ず取扱説明書を参照の上、作業を行っ

てください。

サービスをおこなう前に、このサービスマニュアルを

必ずお読みください。本機は、火災、感電、けがなど

に対する安全性を確保するために、さまざまな配慮を

おこなっており、また法的には「電気用品安全法」に

もとづき、所定の許可を得て製造されております。

従ってサービスをおこなう際は、これらの安全性が維

持されるよう、このサービスマニュアルに記載されて

いる注意事項を必ずお守りください。

●

本機の仕様は性能改良のため、予告なく変更すること

があります。

●

補修用性能部品の保有期間は、製造打切後8年です。

注意

For Japan & Europe model

Ver. 1

AVR-550SD

SAFETY PRECAUTIONS

The following check should be performed for the continued protection of the customer and service technician.

LEAKAGE CURRENT CHECK

Before returning the unit to the customer, make sure you make either (1) a leakage current check or (2) a line to chassis

resistance check. If the leakage current exceeds 0.5 milliamps, or if the resistance from chassis to either side of the

power cord is less than 460 kohms, the unit is defective.

(1)

(2)

500V

(1)

(2)

AVR-550SD

LEVEL DIAGRAM

AVR-550SD

BLOCK DIAGRAM

AVR-550SD

SEMICONDUCTORS

Only major semiconductors are shown, general semiconductors etc. are omitted to list.

主な半導体を記載しています。汎用の半導体は記載を省略しています。

1. IC’s

Note: Abbreviation ahead of IC No. indicates the name of P.W.B., etc.

注 ): ICNo. の前の記号は、基板の名称を表します。

MAIN: AUDIO DIGITAL P.W.B.

FRONT: FRONT P.W.B.

SMPS: SMPS P.W.B.

VIDEO: VIDEO P.W.B.

I/O: INPUT/OUT PUT P.W.B.

ICE1QS01 (SMPS:IC1)

Pin Assignmen

Block Diagram

N.C.

PCS

RZI

SRC

VCC

OUT

GND

OFC

RZI

UVLO

SET

CLR

Reference

Voltage and

Current

GND

OUT

Power

Driver

Ringing

Suppression

Time

25mV

OFC

PCS

SRC

VCC

Burst-Mode

3.5V

4.4V

4.8V

20V Overvoltage

Protection

Start

Digital Processing

50µs Timer

50ms Timer

ZC-Counter

UP/DO-Counter

Latch

Primary

Regulation

SET

CLR

1V +

Foldback

Point Corr.

1.5V

5.7V

20k

AVR-550SD

ICE2B265 (SMPS:IC2)

ICE2B0565 (SMPS:IC3)

Pin Assignmen

Block Diagram

VCCFB

Is ens e

Dr ain

Sof tS

N.C

GND

Dr ain

Thermal

Shutdown

Tj>140°C

Internal

Bias

Voltage

Reference

Leading Edge

Blanking

200ns

Undervoltage

Lockout

Oscillator

Duty Cycle

max

Current-Limit

Comparator

x3.65

Soft-Start

Comparator

Current Limiting

PWM OP

Improved Current Mode

Soft Start

13.5V

8.5V

6.5V

16.5V 4.0V

RFB

6.5V

Protection Unit

Power-Down

Reset

Power-Up

Reset

Power Management

CSoft-Start

21.5-100kHz

CoolSET™-F2

Spike

Blanking

PWM

Comparator

Error-Latch

5.3V

4.8V

RSoft-Start

Gate

Driver

Vcsth

Propagation-Delay

Compensation

PWM-Latch

0.72

Clock

UFB

fosc

100kHz

21.5kHz

Standby Unit

RSense

0.8V

0.3V

10k

5.6V

CoolMOS™

Isense

GND

SoftS

VCC Drain

6.5V

5.3V

4.8V

4.0V

AVR-550SD

TAS5076 (MAIN: IC100)

Pin Assignment

Block Diagram

22 23

VREGB_CAP

DVDD_RCL

DVSS_RCL

DVDD_PWM

DVSS_PWM

PWM_AP_4

PWM_AM_4

VALID_4

PWM_BM_4

PWM_BP_4

PWM_AP_5

PWM_AM_5

VALID_5

PWM_BM_5

PWM_BP_5

PWM_AP_6

PWM_AM_6

VALID_6

PWM_BM_6

PWM_BP_6

MCLK_IN

AVDD_PLL

PLL_FLT_OUT

PLL_FLT_RET

AVSS_PLL

VREGA_CAP

DVSS1

RESET

ERR_RCVRY

MUTE

PDN

SDA

SCL

CS0

NC 25 26 27 28

79 78 77 76 7580 74 72 71 7073

29 30 31 32 33

69 68

67 66 65 64

34 35 36 37 38 39 40

63 62 61

NC − No internal connection

AVDD_OSC

XTL_IN

XTL_OUT

AVSS_OSC

DVSS

PWM_AP1

PWM_AM_1

VALID_1

PWM_BM_1

PWM_BP_1

PWM_AP_2

PWM_AM_2

VALID_2

PWM_BM_2

PWM_BP_2

PWM_AP_3

PWM_AM_3

VALID_3

PWM_BM_3

PWM_BP_3

DBSPD

CLIP

SDIN1

SDIN2

SDIN3

MCLK_OUT

SCLK

LRCLK

DVDD

DVSS

VREGC_CAP

DEM_SEL2

DEM_SEL1

M_S

DVSS1

PWM Ch.

Output Control

AVDD_PLL

AVSS_PLL

VREGA_CAP

VREGB_CAP

VREGC_CAP

DVDD_RCL

DVSS_RCL

DVDD_PWM

DVSS_PWM

Power Supply

PLL_FLT_OUT

PLL_FLT_RET

SCLK

LRCLK

MCLKOUT

SDIN1

SDIN2

SDIN3

MCLK_IN

XTAL_OUT

XTAL_IN

DBSPD

SDA

SCL

CSO

PWM_AP_1

PWM_BP_1

PWM_AM_1

Clock,

PLL

and

Serial

Data

I/F

PDN

RESET

MUTE

CLIP

ERR_RCVY

Serial

Control

I/F

Reset,

Pwr Dwn

and

Status

Auto Mute

De-emphasis

Soft Volume

Error Recovery

Soft Mute

Clip Detect

Signal

Processing

PWM

Section

PWM Ch.

M_S

DM_SEL1

DM_SEL2

VALID_1

PWM_BM_1

PWM_AP_2

PWM_BP_2

PWM_AM_2

VALID_2

PWM_BM_2

PWM_AP_3

PWM_BP_3

PWM_AM_3

VALID_3

PWM_BM_3

PWM_AP_4

PWM_BP_4

PWM_AM_4

VALID_4

PWM_BM_4

PWM_AP_5

PWM_BP_5

PWM_AM_5

VALID_5

PWM_BM_5

PWM_AP_6

PWM_BP_6

PWM_AM_6

VALID_6

PWM_BM_6

AVR-550SD

TAS5182 (MAIN: IC102,103,104)

Pin assignments

Block Diagram

DVDD

DVSS

DTC_HS

DTC_LS

OC_HIGH

VRFILT

RESET_AB

RESET_CD

SHUTDOWN

ERR0

ERR1

LOW/HIZ

DVSS

OC_LOW

TEMP

GVSS

GVDD

GLS_A

SLS_A

SHS_A

GHS_A

BST_A

DHS_A

GLS_B

SLS_B

SHS_B

GHS_B

BST_B

DHS_B

GLS_C

SLS_C

SHS_C

GHS_C

BST_C

DHS_C

GLS_D

SLS_D

SHS_D

GHS_D

BST_D

DHS_D

GVDD

GVSS

BST_D

DHS_D

GHS_D

SHS_D

GLS_D

SLS_D

BST_C

DHS_C

GHS_C

SHS_C

GLS_C

SLS_C

BST_B

DHS_B

GHS_B

SHS_B

GLS_B

SLS_B

PWM

Receiver

Timing

and

Control

Gate

Drive

Gate

Drive

BST_A

DHS_A

GHS_A

SHS_A

GLS_A

SLS_A

ProtectionCircuitry Status

Bandgap

Reference

VRFILT

DTC_HS

DTC_LS

OC_HIGH

TEMP

LOW/HIZ

A – Half-Bridge Driver

PWM

Receiver

Timing

and

Control

Gate

Drive

Gate

Drive

PWM

Receiver

Timing

and

Control

Gate

Drive

Gate

Drive

PWM

Receiver

Timing

and

Control

Gate

Drive

Gate

Drive

B – Half-Bridge Driver

C – Half-Bridge Driver

D – Half-Bridge Driver

RESET_AB

RESET_CD

SHUTDOWN

ERR0

ERR1

DVDD

DVSS

GVDD

GVSS

GVDD

OC_LOW

AVR-550SD

AK4588 (MAIN: IC219)

Pin assignments

Block Diagram

(Top View)

CCLK/SCL

CDTI/SD

CSN

DAUX1

SDTI4

SDTI3

SDTI2

SDTI1

XTL1

XTL0

PDN

MASTE

DZF2

DZF1

LOUT4

ROUT4

LOUT3

INT1

BOUT

TVDD

DVDD

DVSS

XTO

XTI

TEST3

MCKO2

MCKO1

COUT

UOUT

VOUT

SDTO2

BICK2

LRCK2

SDTO1

BICK1

LRCK1

CDTO

TEST1

RX1

RX0

AVSS

AVDD

VREFH

VCOM

RIN

LIN

ROUT1

LOUT1

ROUT2

LOUT2

ROUT3

INT0

TX1

TX0

MCLK

VIN

DAUX2

I2C

RX7

CAD1

RX6

CAD0

RX5

TEST2

RX4

PVDD

PVSS

RX3

RX2

Selecto

Clock

Recovery Clock

Generato

DAIF

Decoder

C-3/MPEG

Detect

DEM

PP I/F

udio

I/F

X'tal

Oscillator

PDN

INT0

LRCK2

BICK2

SDTO2

DAUX2

MCKO2

XTOXTI

RPVDDPVSS

CDTI

CDTO

CCLK

CSN

DVDD

DVSS

TVDD

MCKO1

I2C

RX0

RX1

RX2

RX3

RX4

RX5

RX6

RX7

DIT

TX0

Error &

Detect

STATUS

INT1

Q-subcode

buffe

TX1

B,C,U,

VOUT

8 to 3

VIN

Audio

I/F

LPF

LOUT1

ROUT1

LOUT2

ROUT2

LOUT3

ROUT3

DAC DATT

DEM

ADC HPF

RIN

LIN

LRCK1

BICK1

SDTI1

SDTI2

SDTI3

DAUX1

MCLK

LRCK

BICK

SDOUT

SDIN1

SDIN2

SDIN3

MCLK

SDTO1

Format

Converter

SDTI4

SDIN4

LPF

LOUT4

ROUT4

DAC DATT

DEM

DAC DATT

DEM

DAC DATT

DEM

DAC DATT

DEM

DAC DATT

DEM

DAC DATT

DEM

DAC

DATT

DEM

VDD

VSS

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