Getting Started with CY27410/30: 4-PLL Spread-Spectrum Clock Generator
www.cypress.com Document No. 001-94024 Rev.*A 2
Overview
CY27410 is a 4-PLL spread-spectrum clock generator
targeted at consumer, industrial, and networking
applications. CY27410 has two inputs and twelve outputs,
frequencies up to 700 MHz with a low RMS phase jitter of
1 ps max. CY27410 supports value-added features such
as voltage-controlled crystal oscillator (VCXO), frequency
select, and zero/nonzero delay buffer (ZDB/NZDB) modes.
The part is designed to support reference clocks for key
interface standards such as PCI Express
(PCIe) 1.0/2.0/3.0, USB 2.0/3.0 and 10-Gigabit Ethernet
(GbE).
This application note describes how to configure the
device for different applications and device mode
configurations. In addition, the I2C interface of the device,
its signaling levels, and external design considerations are
explained in the application note.
CY27410 has three major modes of operation: clock
generator (CLKGEN) mode, zero-delay buffer (ZDB) mode,
and nonzero-delay (NZDB) buffer. In the Clock Generator
mode, the device generates multiple clock frequencies
using an internal PLL from an external reference clock or
crystal. In the ZDB mode, the device generates the same
clock frequency as input clock, or integer-multiple or
integer-divide frequencies with little delay with respect to
the input. In the NZDB mode, the device bypasses the
PLL and buffers the input signal to outputs with support of
additional dividers.
CY27410 also provides value-added features such as
phase delay of outputs, voltage controller frequency
synthesis (VCFS), spread spectrum, frequency select, and
glitch-free outputs.
Key Specifications
•Input frequencies
•Crystal input : 8 MHz to 48 MHz
•Reference clock : 8 MHz to 250 MHz LVCMOS
•Reference clock : 8 MHz to 700 MHz differential
•Output frequencies
•LVDS, LVPECL, host-clock signal level (HCSL),
current mode logic ((CML) 25 –375 MHz, 400 –
500 MHz, 600 –700 MHz))
•LVCMOS (3 MHz to 250 MHz)
•1 kHz to 8 MHz for one LVCMOS output
•RMS phase jitter < 1 ps max at 12-kHz to 20-MHz
Offset
•PCIe 1.0/2.0/3.0, SATA 2.0, USB 2.0/3.0, 1/10GbE
•Maximum 12 outputs split in two banks of 6 outputs
each.
•Up to 8 differential output pairs (HCSL, LVPECL,
CML, or LVDS)
•Up to 12 LVCMOS outputs
•Up to 75-ps skew for differential outputs within a bank
•Four fractional N-type PLL with
•VCXO (+/-120 ppm)
•Spread-spectrum capability (Logic SS and
Lexmark profile 0.1 to 5% in 0.1% steps, down or
center-spread)
•Supply voltage: 1.8 V, 2.5 V and 3.3 V
•ZDB/NZDB configurations
•I2C-configurable with On-board programming
•Industrial and Automotive grade devices
•48-pin QFN package.
Modes of Operation
CY27410 has CLKGEN, ZDB, and NZDB modes. It can
also be configured in a combination of CLKGEN and ZDB,
CLKGEN and NZDB, and ZDB and NZDB modes.
CLKGEN Mode
Figure 1 shows the PLL block diagram in CLKGEN mode.
In this mode, CY27410 generates multiple clock
frequencies from one reference crystal or clock input. Up
to four unrelated clock frequencies can be generated in
this mode from the four PLLs of the device. Each PLL has
again four independent dividers, so you may generate up
to four different related frequencies from a PLL. Two
frequencies are said to be unrelated if there is no common
multiple for the two clock frequencies within the PLL VCO
range of 2.4 GHz to 3.0 GHz.
Figure 1: Clock Generator Configuration
