Cmsemicon BAT32A237 User manual

BAT32A237 User's Guide |Documentation Usage Instructions

www.mcu.com.cn 1 / 1037 V1.00

BAT32A237 User Manual

Ultra-low power 32-bit microcontroller based on ARM® Cortex®-M0+

Rev1.00

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BAT32A237 User's Guide |Documentation Usage Instructions

www.mcu.com.cn 2 / 1037 V1.00

Documentation Instructions

This manual is the technical reference manual for the BAT32A237 microcontroller product. The technical

reference manual is the application instruction material on how to use this series of products, including the

structure, function description, working mode and register configuration of each functional module.

The technical reference manual is a description of all functional modules of this series of products. If you want

to know the feature description of the product (that is, the functional configuration), you can refer to the respective

data sheet.

The data sheet information is as follows：

BAT32A237xx：BAT32A237_datasheet_vx.x. pdf

Usually in the early stage of chip selection, you shall first check the data sheet to evaluate whether the product

can meet the functional requirements of the design; after basically selecting the required product, you need to check

the technical reference manual to determine whether the working mode of each functional module does meet the

requirement；When determining the selection and entering the programming design stage, you need to read the

technical reference manual in detail to understand the specific implementation and register configuration of each

function. Refer to the data sheet for information on voltages, currents, drive capabilities, and pin assignments when

designing hardware。

For a detailed description of the Cortex-M0+ core, SysTick timer and NVIC, please refer to the respective ARM

documents.

BAT32A237 user manual | Chapter 1 CPU

www.mcu.com.cn 3 / 1037 V1.00

Chapter 1 CPU

1.1 verview

This Chapter provides a brief introduction to the features and debugging features of the ARM Cortex-M0+

kernel on which this product is built. Please refer to the ARM documentation for details.

1.2 Cortex-M0+ core features

⚫ARM Cortex-M0+ processors are 32-bit RISC cores with a 2-stage pipeline that supports privileged and

user modes

⚫Memory Protection Units (MPUs) support 8 separate Zone (region) protection

⚫single cycle hardware multiplier

⚫Nested Vector Interrupt Controller (NVIC)

◼1 Unshielded Interrupt (NMI)

◼Supports 32 Masking Interrupt Requests (IRQs)

◼4 interrupt priority

⚫The system timer SysTick is a 24-bit countdown timer that can be selected for fCLK or fIL count clocks

⚫vector table offset register (VTOR)

◼The software can write VTOR to relocate the start address of the vector table to a different location

◼The default value for this register is 0x0000_0000, with low 8-bit write ignore, read to zero, that is,

offset 256 bytes aligned

1.3 Debug features

⚫2-wire SWD debug interface

⚫Support for pausing, resuming, and single-step execution procedures

⚫Access processor's kernel register and special function register

⚫4 Hardware Breakpoints (BPUs)

⚫Unlimited software breakpoints (BKPT instruction)

⚫2 data observation points (DWT)

⚫Access memory during kernel execution

⚫Micro Trace Cache (MTB) provides a simple instruction execution trace scheme

- MTB shared with user SRAM (0x2000_0000-0x2000_2 FFF zone)

- The base address of the MTB control register is 0x4001_9000

BAT32A237 user manual | Chapter 1 CPU

www.mcu.com.cn 4 / 1037 V1.00

Figure 1-1 Debug Block Diagram for Cortex-M0+

Note: SWD does not work in Deep Sleep mode, please debug in active and sleep mode.

bus matrix

Cortex

M0+

core

Bridge

NVIC

DWT

BPU

MTB

system bus

Cortex

M0+

debug support

MCU

debug support

SWDIO

SWCLK

DBGMCU

AHB

BAT32A237 user manual | Chapter 1 CPU

www.mcu.com.cn 5 / 1037 V1.00

1.4 SWD interface pin

2 GPIO of the product can be used as SWD interface pins that are present in all packages.

Table 1-1 SWD Debug Port Pin

When you do not use the SWD feature, you can disable the SWD by setting the debug stop control register

(DBGSTOPCR).

Bit no.

DBGSTOPCR

SWDIS

Default

Bit no.

DBGSTOPCR

Default

Bit no.

DBGSTOPCR

Default

Bit no.

DBGSTOPCR

FRZEN1

FRZEN0

Default

SWDIS

SWD Debug Interface Disable

SWD debug interface enable. P40 cannot be used as a GPIO in the state where the debugger is connected

(because the ENO and DOUT for that IOBUF are now controlled by the debugger)

The SWD debug interface is disabled. P40 can be used as GPIO

FRZEN0

In the state where the debugger is connected and the CPU is in the debug state (HALED=1), the timer is the

peripheral module action/stop note 1

peripheral action

peripheral stop

FRZEN1

In the state where the debugger is connected and the CPU is in the debug state (HALED=1), the

communication system peripheral module action/stop note 2

peripheral action

peripheral stop

Note 1: The timer system peripheral module of the product includes: Universal timer unit Timer4, timer A, timer B,

timer C, and timer M

Note 2: The communication system peripheral module of this product includes: Communication Serial

Communication Unit, Serial IICA

SWD port name

Debug Function

pin assignment

SWCLK

serial clock

P137

SWDIO

Serial Data Input/Output

P40

BAT32A237 user manual | Chapter 1 CPU

www.mcu.com.cn 6 / 1037 V1.00

1.5 ARM reference document

The built-in debugging features in the Cortex®-M0+ kernel are part of the ARM® CoreSight design suite. For

documentation, refer to:

⚫Cortex®-M0+ Technical Reference Manual (TRM)

⚫ARM® Debug Interface V5

⚫ARM® CoreSight Design Kit Version r1p1 Technical Reference Manual

⚫ARM® CoreSi-M0+ Technical Reference Manual

BAT32A237 user manual | Chapter 2 Pin function

www.mcu.com.cn 7 / 1037 V1.00

Chapter 2 Pin function

2.1 port function

Refer to datasheet for each product family.

2.2 port multiplex

Refer to datasheet for each product family.

BAT32A237 user manual | Chapter 2 Pin function

www.mcu.com.cn 8 / 1037 V1.00

2.3 Register for controlling port function

Control the port through the following registers.

Port Mode Registers (PMxx)

Port Registers (Pxx)

Pull-up resistor selection registers (PUxx)

Port Input Mode Registers (PIMx)

Port Output Mode Registers (POMx)

Port Mode Control Registers (PMCxx)

Peripheral I/O Redirection Registers (PIORx)

Global Digital Input Disable Register (GDIDIS)

Note: The assigned registers and bits differ depending on the product. Refer to for registers and bits allocated by each

productTable 2-1. You must set an initial value for unassigned bits.

Table 2-1 PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and bits (1/2)

Port

bit name

PMxx

Pxx

PUxx

PIMxx

POMxx

PMCxx

Port 0

PM00

P00

PU00



POM00

PMC00Note 1

○

PM01

P01

PU01

PIM01



PMC01Note 1

○

PM02

P02

PU02



POM02

PMC02

○



PM03

P03

PU03

PIM03

POM03

PMC03

○



PM04

P04

PU04

PIM04

POM04

PMC04

○



PM05

P05

PU05



○



PM06

P06

PU06



○



Port 1

PM10

P10

PU10

PIM10

POM10

PMC10

○

PM11

P11

PU11



POM11

PMC11

○

PM12

P12

PU12



PMC12Note 2

○

PM13

P13

PU13



POM13

PMC13Note 2

○

PM14

P14

PU14

PIM14

POM14

PMC14Note 2

○

PM15

P15

PU15

PIM15

POM15



○

PM16

P16

PU16

PIM16



○



PM17

P17

PU17

PIM17

POM17



○



Port 2

PM20

P20



PMC20

○

PM21

P21



PMC21

○

PM22

P22



PMC22

○

PM23

P23



PMC23

○



PM24

P24



PMC24

○



PM25

P25



PMC25

○



PM26

P26



PMC26

○



PM27

P27



PMC27

○



Note: 1. Products with 24-48 pins only.

2. Products with 24-64 pins only.

BAT32A237 user manual | Chapter 2 Pin function

www.mcu.com.cn 9 / 1037 V1.00

Table 2-2: PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and bits (2/2)

Port

bit name

PMxx

Pxx

PUxx

PIMxx

POMxx

PMCxx

Port 3

PM30

P30

PU30

PIM30

POM30



○



PM31

P31

PU31

PIM30 Note 1

POM31 Note 1



○



Port 4

PM40

P40

PU40



○

PM41

P41

PU41



○



PM42

P42

PU42



○



PM43

P43

PU43



○



Port 5

PM50

P50

PU50

PIM50

POM50



○

PM51

P51

PU51



POM51



○

PM52

P52

PU52



○



PM53

P53

PU53



○



PM54

P54

PU54



○



PM55

P55

PU55

PIM55

POM55



○



Port 6

PM60

P60



○



PM61

P61



○



PM62

P62



○



PM63

P63



○



Port 7

PM70

P70

PU70



○



PM71

P71

PU71



POM71



○



PM72

P72

PU72



○

PM73

P73

PU73



○

PM74

P74

PU74

PIM74 Note 1

POM74



○



○



PM75

P75

PU75



○



○



PM76

P76

PU76



○



PM77

P77

PU77



○



Port 12

PM120

P120

PU120



PMC120

○



P121



○



P122



○



P123



○



P124



○



Port 13



P130



○



PM136

P136

PU136



○



○

PM137

P137

PU137



○

Port 14

PM140

P140

PU140



○



○



PM141

P141

PU141



○



PM146

P146

PU146



PMC146

○



PM147

P147

PU147



PMC147

○

Note: 1. Products with 32 pins only.

BAT32A237 user manual | Chapter 2 Pin function

www.mcu.com.cn 10 / 1037 V1.00

2.3.1 Port Mode Register (PMxx)

This is a register that sets the port input/output in bits. After the reset signal is generated, the values of these

registers become "FFH". When using a port pin as a pin for a multiplexing function, it must be configured according

to reference to "2.5 Register settings when using multiplexing function.

the offset address is shown in the figure below.

Figure 2-1 Port mode register format

symbol

offset

After

Reset

R/W

PM0

PM06

PM05

PM04

PM03

PM02

PM01

PM00

0x320

FFH

R/W

PM1

PM17

PM16

PM15

PM14

PM13

PM12

PM11

PM1 0

0x321

FFH

R/W

PM2

PM27

PM26

PM25

PM24

PM23

PM22

PM21

PM20

0 x322

FFH

R/W

PM3

PM31

PM3 0

0x323

FFH

R/W

PM4

PM43

PM42

PM 41

PM4 0

0x324

FFH

R/W

PM5

PM55

PM54

PM53

PM52

PM 51

PM50

0x325

FFH

R/W

PM6

PM63

PM62

PM61

PM60

0x326

FFH

R/W

PM7

PM77

PM76

PM75

PM74

PM73

PM72

PM 71

PM70

0x327

FFH

R/W

PM12

PM120

0x32C

FFH

R/W

PM13

PM137

PM136

PM130

0x32D

FEH

R/W

PM14

PM147

PM146

PM141

PM140

0x32E

FFH

R/W

PMmn

Selection of Input/Output Modes of Pmn Pins (m=0~7,12~14, n=0~7)

Output mode (used as output port (output buffer ON))

Input mode (used as input port (output buffer OFF))

Note: You must set an initial value for unassigned bits.

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