Analog Devices ADSP-219 Series Application guide

ADSP-219x/2192 DSP Hardware Reference B-1

B ADSP-2192 DSP PERIPHERAL

REGISTERS

Figure B-0.

Table B-0.

Listing B-0.

Overview

The DSP has general-purpose and dedicated registers in each of its func-

tional blocks. The register reference information for each functional block

includes bit definitions, initialization values, and (for I/O processor regis-

ters) memory-mapped addresses. Information on each type of register is

available at the following locations:

•“Core Status Registers” on page A-8

•“Computational Unit Registers” on page A-16

•“Program Sequencer Registers” on page A-19

•“Data Address Generator Registers” on page A-26

•“Peripheral Registers” on page B-2

When writing DSP programs, it is often necessary to set, clear, or test bits

in the DSP’s registers. While these bit operations can be done by referring

to the bit’s location within a register or (for some operations) the register’s

address with a hexadecimal number, it is much easier to use symbols that

correspond to the bit’s or register’s name.

For convenience and consistency, Analog Devices provides header files

that define these bit and register definitions (def2192_IO.h,

def2192_PCI.h, def2192_USB.h, def2192-12.h, and def219x.h). Note

that the def2192-12.h file also contains the definitions from the IO, PCI,

and USB header files.

Peripheral Registers

B-2 ADSP-219x/2192 DSP Hardware Reference

A sample of def219x.h is shown in “Register & Bit #Defines File”on

page A-29, and a sample of def2192-12.h is shown in “Register and Bit

#Defines File”on page B-95.

LMany registers have reserved bits. When writing to a register, pro-

grams may clear (write zero to) the register’s reserved bits only.

Peripheral Registers

There are three groups of registers for the ADSP-2192:

•“ADSP-2192 DSP Core Registers”on page A-1

•“ADSP-2192 System Control Registers”on page B-6

•“ADSP-2192 Peripheral Device Control Registers”on page B-11

This appendix describes system control registers and peripheral device

control registers. A general description of DSP peripheral architecture,

which follows, provides an overview of peripheral registers.

ADSP-219x/2192 DSP Hardware Reference B-3

ADSP-2192 DSP Peripheral Registers

DSP Peripherals Architecture

Figure B-1 shows the DSP’s on-chip peripherals, which include the Host

port (PCI or USB), AC’97 port, JTAG test and emulation port, flags, and

interrupt controller.

Figure B-1. ADSP-2192 Dual-Core DSP Block Diagram

The ADSP-2192 can respond to up to fourteen interrupts at any given

time. A list of these interrupts can be found in the table “Interrupt Vectors

for an ADSP-2192 DSP Core”on page 6-14.

The AC’97 codec port on the ADSP-2192 provides a complete synchro-

nous, full-duplex serial interface. This interface completely supports the

AC’97 standard.

The ADSP-2192 provides up to eight general-purpose I/O pins, which are

programmable as either inputs or outputs. These pins are dedicated gen-

eral-purpose programmable flag pins.

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Peripheral Device Register Groups

B-4 ADSP-219x/2192 DSP Hardware Reference

Peripheral Device Register Groups

The registers that control FIFO DMA transfers are accessible only from

within the DSP. They are defined as part of the Core Register Space.

Summary

Each of the DSPs integrated within the ADSP-2192 and the interfaces

(PCI, USB Sub-ISA, Cardbus) needs to be capable of controlling and

monitoring a variety of registers external to the DSP core. This section

describes how the DSPs access these Peripheral Device Control (PDC)

registers. The operation of the Peripheral Device Control (PDC) Bus that

connects the DSPs and Interfaces to the PDC Registers is also described in

this section.

Writes to AC’97 codec registers are posted, but only one may complete

per AC’97 frame. Up to two writes may be pending at any one time. The

first write completes with zero PDC wait states. A second write launched

immediately after the first incurs PDC wait states equivalent to a few

AC’97 BITCLKs. A third write in a row blocks for an entire AC’97 frame.

Use the Frame interrupt to time AC’97 codec writes out to one per frame,

assuring that they will all complete with zero wait states.

Reads from AC’97 codec registers must always wait for the data to be

returned. A read must also wait for any pending AC’97 codec register

writes to complete before it can begin. In the best case, a read takes one

full AC’97 frame plus another three AC’97 slots (25.39 µs, or approxi-

mately 3,744 DSP cycles). This is also the typical case when the AC’97

Frame Interrupt is used to time the Read.

The worst case AC’97 read time is four frames plus three slots (87.89 µs,

or approximately 12,960 DSP cycles). This occurs only when there are

already two AC’97 codec register writes pending just after the start of a

frame.

ADSP-219x/2192 DSP Hardware Reference B-5

ADSP-2192 DSP Peripheral Registers

Most AC’97 codec registers may be shadowed, and actual reads should be

rare.

Example

In the worst case, DSP core P1 posts two AC’97 codec register writes just

after the start of a new Frame. DSP core P0 immediately follows with a

read to an AC’97 codec register. DSP core P0 will be unable to compute,

DMA, or interrupt for 87.89 µs. DSP core P1 can compute with data in

its own memory, but cannot communicate with DSP core P0 or access any

PDC bus register for 87.89 µs. The external bus interface can communi-

cate with DSP core P1, but cannot communicate with DSP core P0 or

access any PDC bus register for 87.89 µs. In the state, the entire

ADSP-2192 system is highly constrained.

ADSP-2192 System Control Registers

B-6 ADSP-219x/2192 DSP Hardware Reference

ADSP-2192 System Control Registers

The following tables show the System Control Registers in each DSP core.

Table B-1. ADSP-2192 System Control Registers

Address Register Function

00 B0 Base Register0

01 B1 Base Register1

02 B2 Base Register2

03 B3 Base Register3

04 B4 Base Register4

05 B5 Base Register5

06 B6 Base Register6

07 B7 Base Register7

08 - 0B Reserved

0C DMAPAGE DMA Page Register

0D - 0E Reserved

0F CACTL Cache Control Register

10 STCTL0 FIFO0 Transmit Control Register

11 SRCTL0 FIFO0 Receive Control Register

12 TX0 FIFO0 Transmit Data (TX) register

13 RX0 FIFO0 Receive Data (RX) register

ADSP-219x/2192 DSP Hardware Reference B-7

ADSP-2192 DSP Peripheral Registers

14 - 1F Reserved

20 STCTL1 FIFO1 Transmit Control Register

21 SRCTL1 FIFO1 Receive Control Register

22 TX1 FIFO1 Transmit Data (TX) register

23 RX1 FIFO1 Receive Data (RX) register

24 - 2F Reserved

30 TPERIOD Timer Period Register

31 TCOUNT Timer Counter Register

32 TSCALE Timer Scaling Register

33 TSCALECNT Timer Scale Count Register

34 FLAGS Flags Register

35 - 3F Reserved

40 - 43 Reserved

44 MASTADDR DMA Address, DSP Master DMA

45 MASTNXTADDR DMA Next Address, DSP Master DMA

46 MASTCNT DMA Count, DSP Master DMA

47 MASTCURCNT DMA Current Count, DSP Master DMA

48 TX0ADDR DMA Address, FIFO0 Transmit

49 TX0NXTADDR DMA Next Address, FIFO0 Transmit

Table B-1. ADSP-2192 System Control Registers (Continued)

Address Register Function

ADSP-2192 System Control Registers

B-8 ADSP-219x/2192 DSP Hardware Reference

4A TX0CNT DMA Count, FIFO0 Transmit

4B TX0CURCNT DMA Current Count, FIFO0 Transmit

4C RX0ADDR DMA Address, FIFO0 Receive

4D RX0NXTADDR DMA Next Address, FIFO0 Receive

4E RX0CNT DMA Count, FIFO0 Receive

4F RX0CURCNT DMA Current Count, FIFO0 Receive

50 TX1ADDR DMA Address, FIFO1 Transmit

51 TX1NXTADDR DMA Next Address, FIFO1 Transmit

52 TX1CNT DMA Count, FIFO1 Transmit

53 TX1CURCNT DMA Current Count, FIFO1 Transmit

54 RX1ADDR DMA Address, FIFO1 Receive

55 RX1NXTADDR DMA Next Address, FIFO1 Receive

56 RX1CNT DMA Count, FIFO1 Receive

57 RX1CURCNT DMA Current Count, FIFO1 Receive

58-5F Reserved

60 DBGCTRL Test and Emulation Debug Control Register

61 DBGSTAT Test and Emulation Debug Status Register

62 CNT0 Cycle Counter 0 Register (LSB)

63 CNT1 Cycle Counter 1 Register

Table B-1. ADSP-2192 System Control Registers (Continued)

Address Register Function

ADSP-219x/2192 DSP Hardware Reference B-9

ADSP-2192 DSP Peripheral Registers

STCTLx FIFO Transmit Control Register

These include the STCTL0 and STCTL1 registers in each DSP core.

SRCTLx FIFO Receive Control Register

These include the SRCTL0 and SRCTL1 registers in each DSP core.

64 CNT2 Cycle Counter 2 Register

65 CNT3 Cycle Counter 3 Register (MSB)

66-FF Reserved

1514131211109876543210

FLOW

EMPTY

FULL

LOOP

SDEN

FIP2

FIP1

FIP0

SSEL3

SSEL2

SSEL1

SSEL0

DSP

FLSH

SDEN

SPEN

1514131211109876543210

FLOW

EMPTY

FULL

LOOP

SDEN

FIP2

FIP1

FIP0

SSEL3

SSEL2

SSEL1

SSEL0

DSP

FLSH

SDEN

SPEN

Table B-1. ADSP-2192 System Control Registers (Continued)

Address Register Function

ADSP-2192 System Control Registers

B-10 ADSP-219x/2192 DSP Hardware Reference

xxxADDR DMA Address Register

This group of registers include Rx0ADDR, Rx1ADDR, Tx0ADDR, Tx1ADDR, and MAS-

TADDR registers for each DSP core. Each register is a 16-bit register

containing a 16-bit word.

xxxNXTADDR DMA Next Address Register

This group of registers include Rx0NXTADDR, Rx1NXTADDR, Tx0NXTADDR, Tx1NXTADDR,

and MASTNXTADDR for each DSP core. Each register is a 16-bit register con-

taining a 16-bit word.

xxxCNT DMA Count Register

This group of registers include Rx0CNT, Rx1CNT, Tx0CNT, Tx1CNT, and MASTCNT for

each DSP core. Each register is a 16-bit register containing a 16-bit word.

xxxCURCNT DMA Current Count Register

This group of registers include Rx0CURCNT, Rx1CURCNT, Tx0CURCNT, Tx1CURCNT,

and MASTCURCNT for each DSP core. Each register is a 16-bit register contain-

ing a 16-bit word.

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