Alinx ACU5EV User manual
ZYNQ UltraScale+
FPGA Development Board
ACU5EV
System on Module
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Version Record
Version
Date
Release By
Description
Rev 1.1
2021-04-24
Rachel Zhou
First Release
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Table of Contents
Version Record.......................................................................................................2
Part 1: ACU5EV Core Board Introduction ....................................................... 4
Part 2: ZYNQ Chip.................................................................................................6
Part 3: DDR4 DRAM............................................................................................. 9
Part 4: QSPI Flash.............................................................................................. 16
Part 5: eMMC Flash............................................................................................ 18
Part 6: Clock configuration.................................................................................20
Part 7: LED........................................................................................................... 23
Part 8: Power Supply.......................................................................................... 24
Part 9: ACU5EV Core Board Size Dimension................................................26
Part 10: Board to Board Connectors pin assignment................................... 27
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Part 1: ACU5EV Core Board Introduction
ACU5EV (core board model, the same below) FPGA core board, ZYNQ
chip is based on XCZU5EV-2SFVC784I of XILINX company Zynq UltraScale+
MPSoCs EV Family.
This core board uses 5 Micron DDR4 chips MT40A512M16GE, of which 4
DDR4 chips are mounted on the PS side to form a 64-bit data bus bandwidth
and 4GB capacity. One DDR4 chip is mounted on the PL end, which is a 16-bit
data bus width and a capacity of 1GB. The highest operating speed of DDR4
SDRAM on the PS side can reach 1200MHz (data rate 2400Mbps), and the
highest operating speed of DDR4 SDRAM on the PL side can reach 1066MHz
(data rate 2132Mbps). In addition, a 256MBit QSPI FLASH and an 8GB eMMC
FLASH chip are also integrated on the core board to start storage configuration
and system files.
In order to connect with the carrier board, the four board-to-board
connectors of this core board expand the PS side USB2.0 interface, Gigabit
Ethernet interface, SD card interface and other remaining MIO ports; also
expand 4 pairs of PS MGT high-speed transceiver interface; and almost all IO
ports on the PL side (HP I/O: 96, HD I/O: 84). The wiring between the
XCZU5EV chip and the interface has been processed with equal length and
differential, and the core board size is only 3.15*2.36 (inch), which is very
suitable for secondary development.
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Figure 1-1: ACU5EV Core Board (Front View)
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Part 2: ZYNQ Chip
The FPGA core board ACU5EV uses Xilinx's Zynq UltraScale+ MPSoCs
EV family chip, module XCZU5EV-2SFVC784I. The PS system of the ZU5EV
chip integrates 4 ARM Cortex™-A53 processors with a speed of up to 1.2Ghz
and supports Level 2 Cache; it also contains 2 Cortex-R5 processors with a
speed of up to 500Mhz
The ZU5EV chip supports 32-bit or 64-bit DDR4, LPDDR4, DDR3, DDR3L,
LPDDR3 memory chips, with rich high-speed interfaces on the PS side such as
PCIE Gen2, USB3.0, SATA 3.1, DisplayPort; it also supports USB2.0 , Gigabit
Ethernet, SD/SDIO, I2C, CAN, UART, GPIO and other interfaces. The PL end
contains a wealth of programmable logic units, DSP and internal RAM. .
Figure 2-1 detailed the Overall Block Diagram of the ZU5EV Chip.
Figure 2-1:
Overall Block Diagram of the
ZYNQ ZU5EV
Chip
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The main parameters of the PS system part are as follows:
ARM quad-core Cortex ™-A53 processor, speed up to 1.5GHz, each
CPU 32KB level 1 instruction and data cache, 1MB level 2 cache,
shared by 2 CPUs
ARM dual-core Cortex-R5 processor, speed up to 600MHz, each CPU
32KB level 1 instruction and data cache, and 128K tightly coupled
memory.
Image Video Processor Mali-400 MP2, speed up to 677MHz, 64KB level
2 cache
External storage interface, support 32/64bit DDR4/3/3L, LPDDR4/3
interface
Static storage interface, support NAND, 2xQuad-SPI FLASH.
High-speed connection interface, support PCIe Gen2 x 4, 2 x USB3.0,
Sata 3.1, Display Port, 4 x Tri-mode Gigabit Ethernet
Common connection interfaces: 2 x USB2.0, 2 x SD/SDIO, 2 x UART,
2 x CAN 2.0B, 2 x I2C, 2 x SPI, 4 x 32b GPIO
Power management: Support the four-part division of power supply
Full/Low/PL/Battery
Encryption algorithm: support RSA, AES and SHA.
System monitoring: 10-bit 1Mbps AD sampling for temperature and
voltage detection.
The main parameters of the PL logic part are as follows:
Logic Cells: 256.2K
Flip-flops: 234.24K
Look-up-tables (LUTs): 117.12K
Block RAM
: 5.1Mb
Clock Management Units (CMTs): 4
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DSP Slices: 1248
Video Codec Unit (VCU): 1
PCIE3.0: 2
GTH 12.5Gb/s Transceiver: 4
XCZU5EV-2SFVC784I chip speed grade is -2, industrial grade, package is
SFVC784
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Part 3: DDR4 DRAM
The ACU5EV core board is equipped with 5 Micron (Micron) 1GB DDR4
chips, model MT40A512M16LY-062E, of which 4 DDR4 chips are mounted on
the PS side to form a 64-bit data bus bandwidth and 4GB capacity. One DDR4
chip is mounted on the PL end, which is a 16-bit data bus width and a capacity
of 1GB. The maximum operating speed of the DDR4 SDRAM on the PS side
can reach 1200MHz (data rate 2400Mbps), and the 4 DDR4 storage systems
are directly connected to the memory interface of the PS BANK504. The
highest operating speed of the DDR4 SDRAM on the PL side can reach
1066MHz (data rate 2133Mbps), and a piece of DDR4 is connected to the
BANK64 interface of the FPGA. The specific configuration of DDR4 SDRAM is
shown in Table 3-1 below:
Bit Number
Chip Model
Capacity
Factory
U12,U14,U15,U16
MT40A512M16LY-062E
512M x 16bit
Micron
Table 3-1: DDR4 SDRAM Configuration
The hardware design of DDR4 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR4.
The hardware connection of DDR4 SDRAM on the PS Side is shown in
Figure 3-1:
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Figure 3-1: DDR3 DRAM schematic diagram
The hardware connection of DDR4 SDRAM on the Pl Side is shown in
Figure 3-2:
Figure 3-2: DDR3 DRAM schematic diagram
Table of contents
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