Alinco DJ-S40T User manual
DJ-S40T / E
Service Manual
CONTENTS
SPECIFICATIONS
1) GENERAL ................................................................ 2
2) TRANSMITTER ........................................................ 2
3) RECEIVER ............................................................... 2
CIRCUIT DESCRIPTION
1) Receiver system ....................................................... 3
2) Terminalmitter system ............................................... 4
3) PLL,VCO Circuit....................................................... 4
4) M38224M6M ............................................................ 5
SEMICONDUCTOR DATA
1) M64082A (XA0543) .................................................. 7
2) NMJ2070MT1 (XA210) ............................................. 8
3) NJM2904V (XA0573)................................................ 8
4) NJM2902V-TE1 (XA0596) ........................................ 9
5) TA31136FN (XA0404)............................................... 9
6) UPC2771T (XA0545).............................................. 10
7) CAT24WC16JITE13 (XA0855)................................ 10
8) S-816A30AMC (XA0848)........................................ 10
9) S-80827ALNP (XA0857)......................................... 11
10) MRF9745T1 (XE0034)............................................ 11
11) Transistor, Diode and LED Outline Drawings........... 12
12) LCD Connection ..................................................... 13
EXPLODEDVIEW
1) FrontView............................................................... 14
2) BottomView............................................................ 15
PARTS LIST
MAIN Unit ......................................................... 16~20
SW Unit .................................................................. 20
Mechanical Parts .................................................... 20
Packing................................................................... 20
ADJUSTMENT ...................................................... 21~22
PC BOARDVIEW
1) UP0433(1/2) side A ................................................ 23
2) UP0433(1/2) side B ................................................ 24
3) PTT Unit WIRING ................................................... 25
SCHEMATIC DIAGRAM ............................................. 26
BLOCK DIAGRAM...................................................... 27
ALINCO,INC.
2
SPECIFICATIONS
1) GENERAL
Frequency coverage T : TX 430 ~ 449.995MHz RX 410 ~ 470MHz
E : TX 430 ~ 439.995MHz RX 430 ~ 439.995MHz
TA : TX 410 ~ 470MHz RX 410 ~ 470MHz
Mode F3E (FM)
Channel steps 5, 10, 12.5, 15, 20, 25, 30 & 50kHz
Memory channels 99 channels+1 CALL channel
Antenna connector SMA (50Ωunbalanced)
Frequency stability ±5 ppm
Microphone impedance 2kΩnominal
Power supply 4.5 ~ 16.0V DC (EXT.termonai)
3.6 ~ 16.0V DC (BATT terminal)
Current 600mA (typical) Transmit high at 1W
150mA (typical) Receive at 280mW
40mA (typical) standby
15mA (typical) Battery save on
Usable temperature range -10 ~ +60° C (14 ~ 140°F)
Dimensions 56 (W) ×102 (H) ×30 (D) mm (with EDH-31)
2.2"(W) ×4.0"(H) ×1.18"(D) inches (with EDH-31)
(Projections not included)
Weight Approx. 160g (5.6oz) (with EBP-53N)
Approx. 95g (3.3oz) (without Battery)
Sub audible Tone(CTCSS) encoder/decoder installed (38tones)
2) TRANSMITTER
Output power Approx. 1.0W EBP-53N installed
Approx. 1.0W 13.8V DC
Approx. 0.6W EDH-31 installed
Approx. 0.2W (LOW)
Modulation system Variable reactance frequency modulation
Spurious emissions -60dB or less
Max. frequency deviation ±5kHz
3) RECEIVER
Receive system Double conversion superheterodyne
Intermediate frequencies 1st 21.7MHz / 2nd 450kHz
Sensitivity(12dB SINAD) -14.0µdB (0.2uV) or less [430 ~ 450MHz]
Selectivity -6dB : 12kHz or more
-60dB : 28kHz or less
Audio output power 280mW or higher( 8Ωload)
200mW (8Ω10% THD)
3
CIRCUIT DESCRIPTION
1) Receiver System
The receiver system is a double superheterodyne system with a 21.7MHz first IF and
a 450kHz second IF.
1.Front End
The signal from the anntena is pssed through low-pass filter and input to RF coil L24
and L17(band pass filter).
The signal from L24 and L17 is amplified by Q9,Q10 and led to the band pass filter,
and let to the first mixer base of Q11.
2. First Mixer
The amplified signal (f0) by Q9,Q10 is mixed eith the first local oscillator signal(f0-21.7MHz)
from the PLL circuit by the first stage mixer Q11 and so is converted into the first IF signal.
The unwanted frequency band of the first IF signal is eliminated by the monolithic
crystal filter FL3,and led to IF amplifier Q8.
3. IF Circuit
The first IF signal is amplified by Q8, and input to pin 16 of IC3, where it is mixed withthe
second local oscillator signal(21.25MHz)and so is converted into the second IF signal(450kHz).
The second IF signal is output from pin3 of IC3, and unwanted frequency band of second IF
signal is eliminated by a ceramic filter FL2.
The resulting signal is then amplified by the second IF limiting amplifier, and detected
by quadrature circuit.the audio signal is output from pin9 of IC3
4.Audio Circuit
The demodulated signal in IF IC3 contains the audio signal and CTCSS signal .
CTCSS signal is passed through the low-pass filter of IC5 and led to TIN port of CPU
to be decoded.The audio signal is input to the main volume VR3 passing through
de-emphasis circuit and high-pass filter circuit of Q19.The signal of which level is
adjusted at the main volume VR3 is input to IC6 of AF amp, then it is amplified to the
level that can drive the speaker.
5.Squelch Circuit
The noise in the audio signal from IC3 is passed through the noise-filter and input to pin8 of IC3.
IC3 includes filter amplifier,high-pass filter and rectifier.
The rectified voltage level from pin14 of IC3 is deliverd to the comparator of the CPU.
The voltage is led to pin1 of CPU and compared with the setting voltage.The squelch
will open if the input voltage is lower than the setting voltage.
During open squelch ,pin11(AFS)of CPU becomes”H”level and pin9(AFP)of CPU
becomes”L”level, AF control signal is being controlled and sounds is outputted from
the speaker.
4
2)Transmitter System
1.Microphone Amplifier
The input signal from built-in or external microphone is led to the microphone mute
circuit Q15,pre-emphasis circuit ,IDC circuit IC4,the signal is input to the maximum
deviation adjustment volume VR2.Then mixed at the addVR2 with the CTCSS tone
signal which is generated by CPU,Then it is input to VCO as the modulation signal.
2.Power Amplifier
The signal from VCO is amplified by IC1 and then passed through the low-pass filter,
the antenna switch circuit and the output low-pass filter.
The unwanted harmonics frequency signal is eliminated by the low-pass filter and
input to the antenna.
3)PLL,VCO Circuit
Output frequency of PLL circuit is set by the serial data from microprocessor.
PLL circuit consists ofVCO Q2,buffer amplifier Q6.
The pulse wave output of chage pump is converted to DC voltage by PLL loop filter
circuit,snd supplied to D2,D15 of varicap diode in VCO unit.
The frequency modulation is executed when audio signal voltage is supplied to the
varicap D3.
When PLL is unlocked,pin10 of IC2 goes to “High”.
5
4) M38224M6M
CPU
Terminal Connection
(TOP VIEW)
6
Terminal function of CPU
No. Pin Name Function I/O Logic
Description
No. Pin Name Function I/O Logic
Description
1 P67 SQL I A/D
Noise level input for squelch
2 P66 KEY I A/D
Key input ( , ,V/M)
3 P65 VOX O Activ high
Power cont.
4 P64 EXTDC I A/D
Ext voltage input
5 P63 BP1 I A/D
Band plan 1
6 P62 TIN I A/D
CTCSS tone input
7 P61 SMT I A/D
S-meter input
8 P60 BATT I A/D
Batt voltage input
9 P57 AFP O Activ low
Audio Amp ON/OFF
10 P56 BEEP I/O Pulse
Beep sound out
11 P55 AFS O Activ high
Audio signal ON/OFF
12 CNTR0 TBST I/O Pulse
Art tone output
13 P53 BP3 I
Band plan 3
14 P52 MONI I Activ low
Monitor key input
15 P51 PSW I Activ low
Power switch input
16 P50 STB O Pulse
Strobe for PLL
17 P47 DATA I/O Pulse
Data for PLL
18 P46 CLK O Pulse
Clock for PLL
19 TxD CTX O Pulse
UART data transmission output
20 RxD CRX I Pulse
UART data reception input
21 P43 SCR I Activ high
Alarm signal input
22 INTO BU I Activ low
Back up signal detection input
23 P41 PTTK I Activ high
PTT signal input
24 P40 BP4 I Activ high
Band plan 4
25 RESET RESET I Activ low
Reset input
26 P71 SCL O Pulse
Serial clock for EEPRPM
27 P70 SDA I/O Pulse
Serial data for EEPRPM
28 Xin XIN I
29 Xout XOUT O
30 Vss GND
CPU GND
31 P27 MMUTE O Activ high
Microphone mute output
32 P26 H/L O Activ high
Power control high=H
33 P25 EXP O Activ low
EXP terminal control
34 P24 FUNC I Activ low
Func key input
35 P23 PTTC O Activ high
Beep sound level control
36 P22 P3C O Activ low
Power supply control for VCO output
37 P21 C3C O Activ high
Power supply control
38 P20 R3C O Activ low
Power supply control for RX
39 P17 T3C O Activ low
Power supply control for TX
40 P16 TON4 O Activ high
Tone output 4
41 P115 TON3 O Activ high
Tone output 3
42 P14 TON2 O Activ high
Tone output 2
43 P13 TON1 O Activ high
Tone output 1
44 SEG26 SEG22 O
LCD SEG 22
45 P115 SHIFT O Activ high
VCO shift output TX=H
46 P10 LAMPC O Activ high
Lamp ON/OFF output
47 SEG23 SEG21 O
LCD SEG 21
48 SEG22 SEG20 O
SEG 20
49 SEG21 SEG19 O
SEG 19
50 SEG20 SEG18 O
SEG 18
51 SEG19 SEG17 O
SEG 17
52 SEG18 SEG16 O
SEG 16
53 P01 CHG O Activ high
Battery charge control
54 P00 MICC O Activ low
TX mic amp power supply outout
55 SEG15 SEG15 O
SEG 15
56 SEG14 SEG14 O
SEG 14
57 SEG13 SEG13 O
SEG 13
58 SEG12 SEG12 O
SEG 12
59 SEG11 SEG11 O
SEG 11
60 SEG10 SEG10 O
SEG 10
61 SEG9 SEG9 O
SEG 9
62 SEG8 SEG8 O
SEG 8
63 SEG7 SEG7 O
SEG 7
64 SEG6 SEG6 O
SEG 6
65 SEG5 SEG5 O
SEG 5
66 SEG4 SEG4 O
SEG 4
67 SEG3 SEG3 O
SEG 3
68 SEG2 SEG2 O
SEG 2
69 SEG1 SEG1 O
SEG 1
70 SEG0 SEG0 O
SEG 0
71 Vcc VDD
72 Vref VDD
73 Avss GND
74 COM3 COM3 O
LCD COM 3
75 COM2 COM2 O
LCD COM 2
76 COM1 COM1 O
LCD COM 1
77 COM0 COM0 O
LCD COM 0
78 VL3 VL3 I
LCD power supply
79 VL2 VL2 I
LCD power supply
80 VL1 VL1 I
LCD power supply
7
SEMICONDUCTOR DATA
1) M64082AGP (XA0543)
DUAL PLL FREQUENCY SYNTHESIZER
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
M64082AGP
SI
Xin
Xout
GND
CONT
Fin2
Vcc
PD1
RST
CPS
Lock
XBo
Vss
PD2
Vc1
Fin1
1 12 14 13
9
10
8
7
15
16
11
6
2
3
4 5
Vcc
Fin1
CONT
Xin
Xout
XBo
SI
RST
CPS
Fin2
GNDVc1
PD2
Vss
Lock
PD1
Programmable divider
for local oscillator 1
Data latch (17 bits)
latch
Phase
comparator
21 pulse counter
OSC 1/2 divider 1/4 divider
through
2-modulus
prescaler
(1/128, 1/129)
2-modulus
prescaler
(1/128, 1/129)
Shift register (21 bits)
Buffer
Programmable divider
for local oscillator 2
Data latch (17 bits)
Data latch (11 or 17 bits)
Programmable divider
for reference frequency
Phase
comparator
Charge
pump
Lock
detection
Charge
pump
8
2) NJM2070MT1 (XA210)
Low Voltage Power Amplifier
Equivalent Circuit
3) NJM2904V-TE1 (XA0573)
9
4) NJM2902V-TE1 (XA0596)
Quad Single Supply Operational Amplifier
5) TA31136FN (XA0404)
Low Power FM IF
10
6) UPC2771T(XA0545)
Terminal Connection
(Top View)
C2H
3
2
1
4
5
6
1: INPUT
2: GND
3: GND
4: OUTPUT
5: GND
6:Vcc
7) CAT24WC16JITE13 (XA0855)
A0
A1
A2
Vss SDA
SCL
WP
Vcc Name Function
Vss Ground
A0..A2 User Configurable Chip Selects
SDA Serial Address/Data I/O
SCL Serial Clock
WP Write Protect Input
Vcc 2.5V~6.0V Power Supply
PDIP
8) S-816A30AMC (XA0848)
41
32
5
OUT
R =0.3Ω
IN
CL
EXT
IN
V
ON/OFF
OUT
V
SS
V
S-816A
~
SOT-23-5
Top view
1
54
23
MC
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