Aeroflex Gaisler RT-SPW-ROUTER User manual

Radiation-Tolerant 10x SpaceWire Router

Radiation Tolerant 6x SpaceWire Router with PCI

RT-SPW-ROUTER

Data Sheet and User’s Manual

GAISLER

Features

• SpaceWire Router compliant

with ECSS-E-ST-50-12C

• Non-blocking switch-matrix

connecting any input to any output

• Packet Distribution

• Group Adaptive Routing

• Path, Logical and Regional Logical addressing

• Two priority levels for output port arbitration

• Conﬁguration port using RMAP, compliant with

ECSS-E-ST-50-52C

• 8x SpaceWire ports, full duplex, on-chip or off-

chip LVDS transceivers

• 2x external FIFO ports, 9-bit wide data paths

• Possible to cascade two routers without glue

logic via the FIFO ports

• 2x internal AMBA ports with DMA and RMAP

• PCI Initiator/Target interface, 32-bit, 33 MHz

• System-time distribution via all ports

• Timers on all ports to prevent deadlock

• Fault-tolerant design

Description

The Radiation-Tolerant SpaceWire

Router family is available as standard

components using the Actel RTAX and

RT ProASIC3 FPGAs. The fault

tolerant design of the router in

combination with the radiation tolerant

FPGA makes it ideally suited for space

and other high-rel applications.

Speciﬁcation

• CCGA484, CQFP352, CCGA624

• Total Ionizing Dose (TID)

to 300 krad (Si, functional)

• Single-Event Latch-Up Immunity

(SEL) to LETTH > 117 MeV-cm2/mg

• Immune to Single-Event Upsets

(SEU) to LETTH > 37 MeV-cm2/mg

• 1.2-1.5V, 2.5V & 3.3V supply,

500 mW consumption (TBD)

• Up to 200 MBPS on SpaceWire links

Applications

The router implements a routing switch

as deﬁned in the ECSS-E-ST-50-12C

SpaceWire links, nodes, routers and

networks standard, supporting all

mandatory and optional features.

Therouterimplementsuptotenexternal

routing ports and the mandatory

conﬁguration port.

The conﬁguration port provides access

toconﬁguration andstatus registers,and

the routing table using the Remote

Memory Access Protocol (RMAP) as

deﬁned in the ECSS-E-ST-50-52C

protocol standard.

The router also fully supports the

ECSS-E-ST-50-51C SpaceWire

protocol identiﬁcation standard.

An optional PCI Initiator/Target

interface is available.

AEROFLEX GAISLER 2 RT-SPW-ROUTER

Table of contents

1 Introduction..............................................................................................................................5

1.1 Overview .................................................................................................................................................5

1.2 Standard conﬁgurations...........................................................................................................................5

1.3 Signal overview.......................................................................................................................................6

2 Architecture..............................................................................................................................7

2.1 Cores........................................................................................................................................................7

2.2 Interrupts .................................................................................................................................................7

2.3 Memory map ...........................................................................................................................................8

2.4 Plug & play information..........................................................................................................................8

2.5 Speciﬁcations...........................................................................................................................................9

2.6 Signals ...................................................................................................................................................10

3 SpaceWire router....................................................................................................................12

3.1 Overview ...............................................................................................................................................12

3.2 Operation...............................................................................................................................................12

3.2.1 Port numbering........................................................................................................................12

3.2.2 Routing table...........................................................................................................................12

3.2.3 Output port arbitration ............................................................................................................13

3.2.4 Group adaptive routing ...........................................................................................................13

3.2.5 Packet distribution...................................................................................................................14

3.2.6 Port disable..............................................................................................................................14

3.2.7 Timers .....................................................................................................................................14

3.2.8 On-chip memories...................................................................................................................16

3.2.9 System time-distribution.........................................................................................................17

3.2.10 Invalid address error................................................................................................................17

3.2.11 Global conﬁguration features..................................................................................................17

3.3 SpaceWire ports.....................................................................................................................................18

3.4 FIFO ports .............................................................................................................................................18

3.4.1 Transmitter..............................................................................................................................18

3.4.2 Receiver...................................................................................................................................19

3.4.3 Time-code transmit .................................................................................................................19

3.4.4 Time-code receive...................................................................................................................20

3.4.5 Bridge mode............................................................................................................................20

3.5 AMBA ports..........................................................................................................................................21

3.5.1 Overview.................................................................................................................................21

3.5.2 Operation.................................................................................................................................21

3.5.3 Receiver DMA channels .........................................................................................................23

3.5.4 Transmitter DMA channels.....................................................................................................29

3.5.5 RMAP target ...........................................................................................................................32

3.5.6 AMBA interface......................................................................................................................34

3.5.7 Registers..................................................................................................................................37

3.6 Conﬁguration port .................................................................................................................................43

3.6.1 AMBA AHB slave interface ...................................................................................................43

3.6.2 Write commands.....................................................................................................................44

3.6.3 Read commands......................................................................................................................44

3.6.4 RMW commands ....................................................................................................................44

3.7 Registers................................................................................................................................................48

3.7.1 Reset value deﬁnitions............................................................................................................48

3.7.2 Register type deﬁnitions..........................................................................................................48

AEROFLEX GAISLER 3 RT-SPW-ROUTER

3.8 Signal deﬁnitions and reset values ........................................................................................................56

3.9 Timing ...................................................................................................................................................58

4 SpaceWire encoder-decoder...................................................................................................60

4.1 Overview ...............................................................................................................................................60

4.2 Operation...............................................................................................................................................60

4.2.1 Overview.................................................................................................................................60

4.2.2 Link-interface FSM.................................................................................................................60

4.2.3 Transmitter..............................................................................................................................61

4.2.4 Receiver...................................................................................................................................61

4.2.5 Time interface .........................................................................................................................62

4.3 Receiver interface..................................................................................................................................63

4.3.1 Link errors...............................................................................................................................63

4.4 Transmitter interface..............................................................................................................................63

4.4.1 Link errors...............................................................................................................................64

4.5 Registers................................................................................................................................................64

5 PCI Initiator/Target ................................................................................................................65

5.1 Overview ...............................................................................................................................................65

5.2 Operation...............................................................................................................................................65

5.2.1 PCI Initiator.............................................................................................................................65

5.2.2 PCI Target ...............................................................................................................................66

5.2.3 Conﬁguration ..........................................................................................................................66

5.2.4 Byte access..............................................................................................................................67

5.2.5 Error response.........................................................................................................................67

5.2.6 Interrupt controller (generation of PCI interrupt)...................................................................67

5.3 Registers................................................................................................................................................68

5.4 Signal deﬁnitions and reset values ........................................................................................................71

5.5 Timing ...................................................................................................................................................72

6 Status Registers......................................................................................................................73

6.1 Overview ...............................................................................................................................................73

6.2 Operation...............................................................................................................................................73

6.2.1 Errors.......................................................................................................................................73

6.2.2 Correctable errors....................................................................................................................73

6.2.3 Interrupts.................................................................................................................................73

6.3 Registers................................................................................................................................................73

7 Serial Debug Interface............................................................................................................75

7.1 Overview ...............................................................................................................................................75

7.2 Operation...............................................................................................................................................75

7.2.1 Transmission protocol.............................................................................................................75

7.2.2 Baud rate generation ...............................................................................................................76

7.3 Registers................................................................................................................................................76

7.4 Signal deﬁnitions and reset values ........................................................................................................77

7.5 Timing ...................................................................................................................................................77

8 JTAG Debug Interface............................................................................................................78

8.1 Overview ...............................................................................................................................................78

8.2 Operation...............................................................................................................................................78

8.2.1 Transmission protocol.............................................................................................................78

8.3 Registers................................................................................................................................................79

AEROFLEX GAISLER 4 RT-SPW-ROUTER

8.4 Signal deﬁnitions and reset values ........................................................................................................79

8.5 Timing ...................................................................................................................................................79

9 Clock generation....................................................................................................................80

9.1 Overview ...............................................................................................................................................80

9.2 Signal deﬁnitions and reset values ........................................................................................................80

9.3 Timing ...................................................................................................................................................80

10 Reset generation.....................................................................................................................81

10.1 Overview ...............................................................................................................................................81

10.2 Signal deﬁnitions and reset values ........................................................................................................81

10.3 Timing ...................................................................................................................................................81

11 AMBA AHB controller with plug&play support...................................................................82

11.1 Overview ...............................................................................................................................................82

11.2 Operation...............................................................................................................................................82

11.2.1 Arbitration...............................................................................................................................82

11.2.2 Decoding.................................................................................................................................82

11.2.3 Plug&play information ...........................................................................................................82

11.3 Registers................................................................................................................................................83

12 AMBA AHB/APB bridge with plug&play support...............................................................84

12.1 Overview ...............................................................................................................................................84

12.2 Operation...............................................................................................................................................84

12.2.1 Decoding.................................................................................................................................84

12.2.2 Plug&play information ...........................................................................................................84

13 Electrical description .............................................................................................................85

13.1 Absolute maximum ratings ...................................................................................................................85

13.2 Operating conditions .............................................................................................................................85

13.3 Input voltages, leakage currents and capacitances................................................................................85

13.4 Output voltages, leakage currents and capacitances..............................................................................85

13.5 Clock Input voltages, leakage currents and capacitances......................................................................85

13.6 Power supplies.......................................................................................................................................85

14 Mechanical description..........................................................................................................86

14.1 Component and package .......................................................................................................................86

14.2 Pin assignment.......................................................................................................................................86

14.3 RTAX2000S/SL speciﬁc pins - CQ352 package...................................................................................94

14.4 RTAX2000S/SL speciﬁc pins - CG624 package...................................................................................95

14.5 RT3PE3000L speciﬁc pins - CG484 package.......................................................................................96

15 Reference documents.............................................................................................................97

16 Ordering information .............................................................................................................98

17 Change record........................................................................................................................99

AEROFLEX GAISLER 5 RT-SPW-ROUTER

1 Introduction

1.1 Overview

The SpaceWire Router family is based on a common architecture from which standard conﬁgurations

are derived. The architecture is centered around the a non-blocking switch matrix which can connect

any input port to any output port.

All the addressing modes such as path, logical and regional logical are supported. Group adaptive

routing is fully supported, meaning that both path and logical addresses can be individually conﬁg-

ured to use from one up to all ports. A unique feature is the support for packet distribution, which can

be used to implement multicast and broadcast addresses. Output ports are arbitrated using two priority

levels with a round-robin scheme within each level.

The 10x SpaceWire router implements 8 external SpaceWire ports and 2 external FIFO ports. The

SpaceWire and FIFO interfaces are directly connected to the switch matrix.

The 6x SpaceWire router implements 4 external SpaceWire ports and a PCI initiator and target inter-

face (32-bit, 33 MHz) accessed via two internal AMBA ports with DMA and RMAP. In this conﬁgu-

ration, the AMBA Advanced High-speed Bus (AHB), to which the AMBA ports and the PCI interface

are connected, is used for high-speed communication between the switch matrix and the external PCI

interface. Supporting low-bandwidth items, such as conﬁguration registers, are connected to the

AMBA Advanced Peripheral Bus (APB) which is accessed through an AHB to APB bridge.

The full SpaceWire router architecture includes the following modules: SpaceWire Router, PCI Initia-

tor/Target Interface, AMBA AHB Debug UART and AMBA AHB Status Register.

1.2 Standard conﬁgurations

Due to resource limitations, it is not possible to ﬁt the full SpaceWire router architecture on a single

device. Therefore, sub-set conﬁgurations have been deﬁned to suit applications with different inter-

facing needs. Table 1 below shows which functions are available in each of the conﬁgurations.

Table 1. Standard conﬁgurations

Conﬁguration name 10x SpaceWire Router 6x SpaceWire Router with PCI

Conﬁguration ID (CID) 1 2

SpaceWire Ports 8 4

FIFO Ports 2

AMBA Ports with RMAP 2

Conﬁguration port with RMAP Yes Yes

Conﬁguration port with AMBA Yes

PCI Initiator/Target and Interrupt Controller Yes

AMBA Status Register Yes

UART Debug Link Yes

JTAG Debug Link

FPGA and Package Actel RTAX2000S CCGA624 Actel RTAX2000S CCGA624

Actel RTAX2000S CQFP352 Actel RTAX2000S CQFP352

Actel RT3PE3000L CCGA484

SpaceWire Physical Layer LVTTL / LVDS (on-chip) LVTTL / LVDS (on-chip)

AEROFLEX GAISLER 6 RT-SPW-ROUTER

1.3 Signal overview

Figure 1. Signal overview

dsutxdsurx

clk

resetn

rxclk

spw_rxdp[]

spw_rxdn[]

spw_rxsp[]

spw_rxsn[]

spw_txdp[]

spw_txdn[]

spw_txsp[]

spw_txsn[]

SpaceWire Links

Clock & Reset

UART Debug Link

dsutck

dsutms

dsutdi

dsutdo

JTAG Debug Link

PCI

pci_clk

pci_gnt

pci_rst

pci_idsel pci_stop

pci_perr

pci_frame

pci_devsel

pci_int

pci_irdy

pci_par

pci_trdypci_ad[31:0]

pci_cbe[31:0]

pci_req

pci_serr

Initiator & Target

txclk

Time-Code Interfaces

timeout0[]

tickout[]tickin[]

timein0[]

timein1[] timeout1[]

timecodeen

FIFO Interfaces

rxread[]

txchar0[]

txchar1[]

enbridge[]

rxchar0[]

rxchar1[]

txwrite[] txfull[]

txafull[]

rxcharav[]

rxaempty[]

Conﬁguration linkrun[]

gerror

reload_timer[]

reload_ps[]

selfaddren

timeren

autodconnect

linkstartreq

instanceid[]

idivisor[]

cfglock

Status

AEROFLEX GAISLER 7 RT-SPW-ROUTER

2 Architecture

2.1 Cores

The common architecture of the SpaceWire router family is based on cores from the GRLIB IP

library. The vendor and device identiﬁers for each core can be extracted from the plug & play infor-

mation. The used IP cores are listed in table 2.

2.2 Interrupts

The SpaceWire router family uses the same interrupt assignment for all conﬁgurations. See the

description of the individual cores for how and when the interrupts are raised. All interrupts are han-

dled by the interrupt controller and forwarded to the PCI bus. Note that this only applies to CID 2.

Table 2. Used IP cores

Core Function Vendor Device CID

AHBCTRL AHB Arbiter & Decoder 0x01 - 2

APBCTRL AHB/APB Bridge 0x01 0x006 2

GRSPWROUTER SpaceWire Router 0x01 - All

AMBA port 0x01 0x8A 2

AMBA conﬁguration port 0x01 0x8B 2

PCIF PCI Initiator/Target 0x01 0x075 2

AHBUART Serial/AHB debug interface 0x01 0x007 2

AHBJTAG JTAG/AHB debug interface 0x01 0x01C -

AHBSTAT AHB failing address register 0x01 0x052 2

Table 3. Interrupt assignment

Core Interrupt Comment CID

GRSPWROUTER 1, 2 AMBA ports 0 and 1, respectively 2

PCIF 3 (spare for future use) 2

AHBSTAT 4 (spare for future use) 2

AEROFLEX GAISLER 8 RT-SPW-ROUTER

2.3 Memory map

The SpaceWire router family uses the same memory map for all standard conﬁgurations. The memory

map shown in table 4 is based on the AMBA AHB address space. Access to addresses outside the

ranges will return an AHB error response. The detailed register layout is deﬁned in the description of

each individual core. Note that this only applies to CID 2.

The control registers of most on-chip peripherals are accessible via the AHB/APB bridge, which is

mapped at address 0x80000000. The memory map shown in table 5 is based on the AMBA AHB

address space. Note that this only applies to CID 2.

2.4 Plug & play information

The LEON3FT RTAX family uses the same plug & play map for all standard conﬁgurations. The plug

& play memory map and bus indexes for AMBA AHB masters are shown in table 6 and is based on

the AMBA AHB address space. Note that this only applies to CID 2.

Table 4. AMBA AHB address range

Core Address range Area CID

PCIF 0x00000000 - 0x3FFFFFFF PCI memory area, 1 GByte 2

APBCTRL 0xFFE00000 - 0xFFEFFFFF APB bridge 2

PCIF 0xFFF00000 - 0xFFF1FFFF PCI I/O area 2

GRSPWROUTER 0xFFFC0000 - 0xFFFC0FFF Conﬁguration area 2

AHB plug&play 0xFFFFF000 - 0xFFFFFFFF 2

Table 5. APB address range

Core Address range Comment CID

GRSPWROUTER 0xFFE00100 - 0xFFE001FF AMBA port 0 2

GRSPWROUTER 0xFFE00200 - 0xFFE002FF AMBA port 1 2

PCIF 0xFFE00300 - 0xFFE003FF 2

AHBUART 0xFFE00400 - 0xFFE004FF 2

AHBJTAG 0xFFE00500 - 0xFFE005FF -

AHBSTAT 0xFFE00600 - 0xFFE006FF 2

APB plug&play 0xFFEFF000 - 0xFFEFFFFF 2

Table 6. Plug & play information for AHB masters

Core Index Function Address range CID

GRSPWROUTER 0 AMBA port 0 0xFFFFF000 - 0xFFFFF01F 2

GRSPWROUTER 1 AMBA port 1 0xFFFFF020 - 0xFFFFF03F 2

PCIF 2 PCI Initiator/Target 0xFFFFF040 - 0xFFFFF05F 2

AHBUART 3 Serial/AHB debug interface 0xFFFFF060 - 0xFFFFF07F 2

AHBJTAG 4 JTAG/AHB debug interface 0xFFFFF080 - 0xFFFFF09F -

AEROFLEX GAISLER 9 RT-SPW-ROUTER

The plug & play memory map and bus indexes for AMBA AHB slaves are shown in table 7 and is

based on the AMBA AHB address space.

The plug & play memory map and bus indexes for AMBA APB slaves are shown in table 8 and is

based on the AMBA AHB address space.

2.5 Speciﬁcations

Note 1: Refer to Actel RTAX and RT ProASIC3 data sheets [RTAX] and [RT3PE] for details.

Note 2: The pre-programmed Actel RTAX and RT ProASIC3 devices are shipped in all quality

levels supported by Actel, as deﬁned in [RTAX] and [RT3PE], respectively.

Table 7. Plug & play information for AHB slaves

Core Index Function Address range CID

APBCTRL 0 AHB/APB Bridge 0xFFFFF800 - 0xFFFFF81F 2

GRSPWROUTER 1 Conﬁguration area 0xFFFFF820 - 0xFFFFF83F 2

PCIF 2 PCI Initiator/Target 0xFFFFF840 - 0xFFFFF85F 2

Table 8. Plug & play information for APB slaves

Core Index Function Address range CID

GRSPWROUTER 0 AMBA port 0 0xFFEFF000 - 0xFFEFF017 2

GRSPWROUTER 1 AMBA port 1 0xFFEFF018 - 0xFFEFF01F 2

PCIF 2 PCI Initiator/Target 0xFFEFF020 - 0xFFEFF027 2

AHBUART 3 Serial/AHB debug interface 0xFFEFF028 - 0xFFEFF02F 2

AHBJTAG 4 JTAG/AHB debug interface 0xFFEFF030 - 0xFFEFF037 -

AHBSTAT 5 AHB failing address register 0xFFEFF038 - 0xFFEFF03F 2

Table 9. Speciﬁcations

Technology Actel RT Axcelerator Actel RT ProASIC3

Device RTAX2000S/SL RT3PE3000L

Link speed 200 MBPS 100 MBPS

Receiver clock 200 MHz 100 MHz

Transmitter clock 100 MHz (DDR) 50 MHz (DDR)

System clock 25 MHz (CID 1) / 33 MHz (CID 2) 25 MHz (CID 1)

PCI clock 33 MHz N/A

Power consumption 500 mW (TBD) 500 mW (TBD)

Package CQFP352, CCGA624 CCGA484

Total Ionizing Dose 1) 300 krad (Si) 15 krad (Si)

Single-Event Latch-Up Immunity (SEL)1) LETTH > 117 MeV-cm2/mg LETTH > 68 MeV-cm2/mg

Single-Event Upsets (SEU) 1) LETTH > 37 MeV-cm2/mg LETTH > 6 MeV-cm2/mg (before TMR)

Supply voltage 1.5 V, 2.5 V & 3.3 V 1.2 V -1.5 V, 2.5 V & 3.3 V

Screening level 2) B, E, EV and PROTO B

AEROFLEX GAISLER 10 RT-SPW-ROUTER

2.6 Signals

The common architecture has the external signals shown in table 10.

Table 10. External signals

Name Usage Direction Polarity CID

clk Main system clock In - All

resetn System reset In Low All

dsutx Debug UART transmit data Out Low 2

dsurx Debug UART receive data In Low 2

dsutck Debug JTAG Clock In - -

dsutms Debug JTAG Mode In High -

dsutdi Debug JTAG Input In High -

dsutdo Debug JTAG Output Out High -

rxclk SpaceWire link receive clock In - All

txclk SpaceWire link transmit clock In - All

spw_rxdp[7:0] Data input, positive In, LVDS High All 1) 3)

spw_rxdn[7:0] Data input, negative In, LVDS Low All 1) 3)

spw_rxsp[7:0] Strobe input, positive In, LVDS High All 1) 3)

spw_rxsn[7:0] Strobe input, negative In, LVDS Low All 1) 3)

spw_txdp[7:0] Data output, positive Out, LVDS High All 1) 3)

spw_txdn[7:0] Data output, negative Out, LVDS Low All 1) 3)

spw_txsp[7:0] Strobe output, positive Out, LVDS High All 1) 3)

spw_txsn[7:0] Strobe output, negative Out, LVDS Low All 1) 3)

spw_rxd[7:0] Data input In, High All 2) 3)

spw_rxs[7:0] Strobe input In High All 2) 3)

spw_txd[7:0] Data output Out High All 2) 3)

spw_txs[7:0] Strobe output Out High All 2) 3)

timecodeen Enable time-code functionality In High 1

tickin[1:0] Tick input signals for FIFO interfaces In High 1

timein0[7:0] Time input signals for FIFO 0 interface In - 1

timein1[7:0] Time input signals for FIFO 1 interface In - 1

tickout[1:0] Tick output signals for FIFO interfaces Out High 1

timeout0[7:0] Time output signals for FIFO 0 interface Out - 1

timeout1[7:0] Time output signals for FIFO 1 interface Out - 1

rxread[1:0] Receiver FIFO read signals for FIFO interfaces In High 1

rxchar0[8:0] Receiver character signals for FIFO 0 interface Out - 1

rxchar1[8:0] Receiver character signals for FIFO 1 interface Out - 1

txwrite[1:0] Transmitter FIFO write signals for FIFO interfaces In High 1

txchar0[8:0] Transmitter character signals for FIFO 0 interface In - 1

txchar1[8:0] Transmitter character signals for FIFO 1 interface In - 1

txfull[1:0] Transmitter full signal for FIFO interfaces Out High 1

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